82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 62

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

discarded, the data stream between the opening flag and the FCS is
divided into blocks. Each block (except the last block) has 32 bytes. The
block will be pushed into a FIFO with one-byte overhead ahead until any
of the following invalid packet conditions occurs:
bits. When the overhead is read from the FIFO, it will be indicated by the
PACK bit. When all valid HDLC blocks are pushed into the FIFO or all
the blocks are read from the FIFO, it will be indicated by the EMP bit.
Functional Description
IDT82P2284
After the stuffed zero (the zero following five consecutive ’One’s) is
• A packet with error FCS;
• The data between the opening flag and the closing flag is less than
• The extracted HDLC packet does not consist of an integral number
• A 7F (Hex) abort sequence is received;
• Address is not matched if the address comparison is enabled. (The
The FIFO depth is 128 bytes. The FIFO is accessed by the DAT[7:0]
M[2:0]:
= 000: A valid short HDLC packet is received, i.e., the data stream between the opening flag and the FCS is less than 32 bytes (including 32
bytes).
= 001: The current block is not the last block of the HDLC packet.
= 010: The current block is the last block of a valid long (more than 32 bytes) HDLC packet.
= 011: Reserved.
= 100: An invalid short HDLC packet is received and the current block is discarded.
= 101: The current block is the last block of an invalid long HDLC packet and the block is discarded.
= 110: Reserved.
= 111: Reserved.
The Length Indication is valid when the M2 bit is zero: Length Indication = N - 1 (N is the number of byte).
Otherwise, the Length Indication is zero.
5 bytes (including the FCS, excluding the flags);
of octets;
address comparison mode is selected by the ADRM[1:0] bits. If
high byte address comparison is required, the high byte address
position (the byte following the opening flag) is compared with the
Figure 15. Overhead Indication In The FIFO
bit 7
M2
M1
M0
overhead (one byte)
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discarded, but the one-byte overhead will still be written into the FIFO.
The overhead consists of the M[2:0] bits and the length indication bits as
shown in Figure 15.
When there are conditions meeting the interrupt sources, the corre-
sponding Interrupt Indication bit will be set to ‘1’ and the Interrupt Indica-
tion bit will be cleared by writing a ‘1’. A ‘1’ in the Interrupt Indication bit
means there is an interrupt. The interrupt will be reported by the INT pin
if its Interrupt Enable bit is ‘1’.
Length Indication
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
If any of the above conditions is detected, the current block will be
The interrupt sources in this block are summarized in Table 30.
value in the HA[7:0] bits, or with ‘0xFC’ or ‘0xFE’. Here the ‘C/R’ bit
position is excluded to compare. If low byte address comparison is
required, the high byte address position is compared with the value
in the LA[7:0] bits. Here the ‘C/R’ bit position is included to com-
pare. If both bytes address comparison is required, the high byte
address position is compared with the value in the HA[7:0] bits, or
with ‘0xFC’ or ‘0xFE’. Here the ‘C/R’ bit position is excluded to
compare. And the low byte position (the byte following the high
byte address position) is compared with the value in the LA[7:0]
bits.
bit 0
February 25, 2008