82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 268

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

E1 RBIF Frame Pulse (048H, 148H, 248H, 348H)
FSINV:
OHD, SMFS, CMFS:
E1 RBIF TS Offset (049H, 149H, 249H, 349H)
TSOFF[6:0]:
are set to TS1 and TS16 overhead indication, the timeslot offset is supported in all the other conditions.
start of the corresponding frame output on the RSDn/MRSDA(MRSDB) pin. The signaling bits on the RSIGn/MRSIGA(MRSIGB) pin are always per-
timeslot aligned with the data on the RSDn/MRSDA(MRSDB) pin.
can be configured from 0 to 127 timeslots (0 & 127 are included).
Programming Information
IDT82P2284
Bit Name
Bit Name
= 0: The receive framing pulse RSFSn is active high.
= 1: The receive framing pulse RSFSn is active low.
In Receive Multiplexed mode, this bit of the four links should be set to the same value.
In Receive Clock Master mode, these bits select what the pulse on RSFSn indicates.
Except that in the Receive Master mode, when the OHD bit (b3, E1-048H,...), the SMFS bit (b2, E1-048H,...) and the CMFS bit (b1, E1-048H,...)
These bits give a binary number to define the timeslot offset. The timeslot offset is between the framing pulse on the RSFSn/MRSFS pin and the
In Non-multiplexed mode, the timeslot offset can be configured from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the timeslot offset
Default
Default
Bit No.
Bit No.
Type
Type
OHD
0
0
0
0
1
Reserved
7
7
SMFS
0
0
1
1
0
CMFS
0
1
0
1
0
TSOFF6
Reserved
R/W
6
0
6
The RSFSn pulses during the first bit of each Basic frame.
The RSFSn pulses during the first bit of each CRC Multi-frame.
The RSFSn pulses during the first bit of each Signaling Multi-frame.
The RSFSn goes high/low during the first bit of each Signaling Multi-frame and goes the opposite during the
second bit of each CRC Multi-frame.
The RSFSn pulses during the TS0 and TS16.
TSOFF5
R/W
5
0
5
TSOFF4
FSINV
R/W
R/W
4
0
4
0
268
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RSFSn Indication
TSOFF3
R/W
OHD
R/W
3
0
3
0
TSOFF2
SMFS
R/W
R/W
2
0
2
0
TSOFF1
CMFS
R/W
R/W
1
0
1
0
February 25, 2008
Reserved
TSOFF0
R/W
0
0
0