82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 36
82P2284BB
Manufacturer Part Number
82P2284BB
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82P2284BB.pdf
(363 pages)
Specifications of 82P2284BB
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
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T1 Digital Multiplexer (DM) Format (T1 only)
up of 12 frames. Each frame consists of one overhead bit (F-bit) and 24
8-bit channels. Except for channel 24, all other channels carry data.
Channel 24 should be ‘0DY11101’. Its Frame Alignment Pattern is
‘100011011100’ in the F-bit. The fixed 6 bits in channel 24 are called
DDS.
Table 14: The Structure of T1 DM
Functional Description
IDT82P2284
Note:
In Channel 24, the ‘D’ bit is used for data link, and the ‘Y’ bit is used for alarm. The other 6 bits are fixed and they are called ‘DDS’ pattern.
The structure of T1 DM is illustrated in Table 14. The T1 DM is made
Frame No. In The T1 DM
10
12
11
1
2
3
4
5
6
7
8
9
Ft
1
0
1
0
1
0
F-Bit (Frame Alignment)
36
DDSC bit. When the DDSC bit is ‘0’, the T1 DM synchronization is
acquired if one correct DDS pattern is received before the first F-bit of a
single correct Frame Alignment Pattern. When the DDSC bit is ‘1’, the
T1 DM synchronization is acquired if a single correct Frame Alignment
Pattern is received and twelve correct DDS patterns before each F-bit of
the correct Frame Alignment Pattern are all detected.
RMFBI bit is set at the first bit of each T1 DM frame.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The synchronization criteria of T1 DM format are selected by the
The T1-DM synchronization is indicated by ‘0’ in the OOFV bit. The
Fs
0
0
1
1
1
0
Channel 24
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
0DY11101
February 25, 2008
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