82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 86

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.18.2 E1 MODE
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
TSDn pin is used to input the data to each link at the bit rate of 2.048
Mb/s. While in the Multiplexed Mode, the data is byte interleaved from
one high speed data stream and inputs on the MTSDA1 (MTSDB1) pins
at the bit rate of 8.192 Mb/s.
transmit system interface is in Transmit Clock Slave mode, otherwise if
the device outputs clock TSCK from itself, the transmit system interface
is in Transmit Clock Master mode.
Table 43: Operating Modes Selection In E1 Transmit Path
Functional Description
IDT82P2284
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. In Transmit Multiplexed mode, two sets of multiplexed data and signaling pins (A and B) are provided for one multiplexed bus. Their functions are the same. One is the backup for the
other. One set is selected by the MTSDA bit when used.
TMUX
In E1 mode, the Transmit System Interface can be set in Non-multi-
In the Non-multiplexed mode, if the TSCK is from outside, the
0
1
TMODE
X
0
1
not both 0s
G56K, GAP
00
X
X
1
Transmit Clock Master Full E1
Transmit Clock Master Fractional E1
Transmit Clock Slave
Transmit Multiplexed
Operating Mode
86
the entire E1 frame, the Transmit System Interface is in Transmit Clock
Master Full E1 mode. If only the clocks aligned to the selected timeslots
are output on TSCKn, the Transmit System Interface is in Transmit
Clock Master Fractional E1 mode.
each link into various operating modes and the pins’ direction of the
transmit system interface in different operating modes.
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
In the Transmit Clock Master mode, if TSCKn outputs pulses during
Table 43 summarizes how to set the transmit system interface of
MTSIGA[1] (MTSDB[1], MTSIGB[1])
TSCKn, TSFSn, TSDn, TSIGn
MTSCK, MTSFS, MTSDA[1],
TSDn, TSIGn
Input
Transmit System Interface Pin
2
February 25, 2008
TSCKn, TSFSn
Output
X
X