82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 344

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table 84: Boundary Scan (BS) Sequence (Continued)
Table 85: TAP Controller State Description
IEEE STD 1149.1 JTAG Test Access Port
IDT82P2284
Test Logic
Run-Test/
DR-Scan
Exit1-DR
Capture-
Shift-DR
Select-
Reset
State
Idle
DR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which
In this state, the test logic is disabled to continue normal operation of the device. During initialization, the device initializes the instruction register with
the IDCODE instruction.
Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is held high for at least 5 rising
edges of TCK. The controller remains in this state while TMS is high.
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The instruction reg-
ister and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller moves to the Select-DR
state.
This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction retains its
previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR state and a scan
sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller moves to the Select-IR-Scan
state.
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction does not
change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in this state and a ris-
ing edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward its serial
output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to
TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low.
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
BS-Cell Name
D2_OUT
D3_OUT
D4_OUT
D5_OUT
D6_OUT
D7_OUT
D_OEN
D2_IN
D3_IN
D4_IN
D5_IN
D6_IN
D7_IN
A[0]
A[1]
BS No.
24
22
20
18
16
14
12
10
23
21
19
17
15
13
11
BS-Cell Type
OUT-CELL
OUT-CELL
OUT-CELL
OUT-CELL
OUT-CELL
OUT-CELL
OUT-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
344
Description
6.3
42 shows its state diagram. A description of each state is listed in
Table 85. Note that the figure contains two main branches to access
either the data or instruction registers. The value shown next to each
state transition in this figure states the value present at TMS at each
rising edge of TCK.
Table 84: Boundary Scan (BS) Sequence (Continued)
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The TAP controller is a 16-state synchronous state machine. Figure -
TEST ACCESS PORT CONTROLLER
BS-Cell Name
(Internal)
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
BS No.
9
8
7
6
5
4
3
2
1
February 25, 2008
BS-Cell Type
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL
IN-CELL