82P2284BB IDT, Integrated Device Technology Inc, 82P2284BB Datasheet - Page 186

• Manufacturer Part Number: 82P2284BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2284BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

T1/J1 Error Insertion (06FH, 16FH, 26FH, 36FH)
DDSINV:
CRCINV:
FsINV:
FtINV:
Programming Information
IDT82P2284
Bit Name
This bit is valid in T1 DM format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit wil invert one 6-bit DDS pattern.
This bit is cleared when the inversion is completed.
This bit is valid in ESF format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one 6-bit CRC pattern.
This bit is cleared when the invertion is completed.
In SF, T1 DM formats, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Fs bit (the F-bit in even frame).
In ESF format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Frame Alignment bit.
In SLC-96 format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Synchronization Fs bit.
This bit is cleared when the inversion is completed.
In SF, T1 DM, SLC-96 formats, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit will invert one Ft bit (the F-bit in odd frame).
This bit is cleared when the inversion is completed.
Default
Bit No.
Type
7
6
Reserved
5
4
186
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
DDSINV
R/W
3
0
CRCINV
R/W
2
0
FsINV
R/W
1
0
February 25, 2008
FtINV
R/W
0
0