DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 384

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
REGISTER 23-1:
DS70616E-page 384
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
Note 1:
R/W-0
ADON
R/W-0
2:
3:
This bit is only available in the ADC1 module. In the ADC2 module, this bit is unimplemented and is read
as ‘0’.
This setting is available in dsPIC33EPXXXMU806/810/814 devices only.
Do not clear the DONE bit in software if ADC Sample Auto-Start is enabled (ASAM = 1).
ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
ADDMABM: DMA Buffer Build Mode bit
1 = DMA buffers are written in the order of conversion. The module provides an address to the DMA
0 = DMA buffers are written in Scatter/Gather mode. The module provides a Scatter/Gather address
Unimplemented: Read as ‘0’
AD12B: 10-bit or 12-bit Operation Mode bit
1 = 12-bit, 1-channel ADC operation
0 = 10-bit, 4-channel ADC operation
FORM<1:0>: Data Output Format bits
For 10-bit operation:
11 = Signed fractional (D
10 = Fractional (D
01 = Signed integer (D
00 = Integer (D
For 12-bit operation:
11 = Signed fractional (D
10 = Fractional (D
01 = Signed Integer (D
00 = Integer (D
SSRC<2:0>
R/W-0
channel that is the same as the address used for the non-DMA stand-alone buffer.
to the DMA channel, based on the index of the analog input and the size of the DMA buffer.
U-0
—
ADxCON1: ADCx CONTROL REGISTER 1
HSC = Set or Cleared by Hardware
W = Writable bit
‘1’ = Bit is set
OUT
OUT
ADSIDL
R/W-0
R/W-0
OUT
OUT
= 0000 00dd dddd dddd)
= 0000 dddd dddd dddd)
= dddd dddd dd00 0000)
= dddd dddd dddd 0000)
OUT
OUT
OUT
OUT
= ssss sssd dddd dddd, where s = .NOT.d<9>)
= ssss sddd dddd dddd, where s = .NOT.d<11>)
= sddd dddd dd00 0000, where s = .NOT.d<9>)
= sddd dddd dddd 0000, where s = .NOT.d<11>)
ADDMABM
SSRCG
R/W-0
R/W-0
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SIMSAM
R/W-0
U-0
—
AD12B
ASAM
R/W-0
R/W-0
 2009-2011 Microchip Technology Inc.
(3)
(1)
x = Bit is unknown
R/W-0, HSC R/C-0, HSC
SAMP
R/W-0
FORM<1:0>
DONE
R/W-0
bit 8
bit 0
(3)