DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 141

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 7-3:
 2009-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
Note 1:
SFTACERR
NSTDIS
R/W-0
R/W-0
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
This bit is available on dsPIC33EPXXXMU806/810/814 devices only.
(1)
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap is disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap is disabled
COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap is disabled
SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
DIV0ERR: Divide-by-zero Error Status bit
1 = Math error trap was caused by a divide by zero
0 = Math error trap was not caused by a divide by zero
DMACERR: DMAC Trap Flag bit
1 = DMAC trap has occurred
0 = DMAC trap has not occurred
MATHERR: Math Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
OVAERR
DIV0ERR
R/W-0
R/W-0
INTCON1: INTERRUPT CONTROL REGISTER 1
(1)
W = Writable bit
‘1’ = Bit is set
OVBERR
DMACERR
R/W-0
R/W-0
(1)
COVAERR
MATHERR
R/W-0
R/W-0
Preliminary
(1)
COVBERR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADDRERR
R/W-0
R/W-0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
OVATE
STKERR
R/W-0
R/W-0
(1)
(1)
(1)
x = Bit is unknown
OVBTE
OSCFAIL
R/W-0
R/W-0
DS70616E-page 141
(1)
COVTE
R/W-0
U-0
—
bit 8
bit 0
(1)