DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 123

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DSPIC33EP512MU810T-I/PT

Manufacturer Part Number
DSPIC33EP512MU810T-I/PT
Description
100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
Manufacturer
Microchip Technology
Series
dsPIC™ 33EPr
Datasheet

Specifications of DSPIC33EP512MU810T-I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
60 MIPs
Connectivity
CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
83
Program Memory Size
512KB (170K x 24)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
24K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33EP512MU810T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
4.6
The
PIC24EPXXXGU810/814 architecture uses a 24-bit-
wide program space and a 16-bit-wide data space. The
architecture is also a modified Harvard scheme, mean-
ing that data can also be present in the program space.
To use this data successfully, it must be accessed in a
way that preserves the alignment of information in both
spaces.
Aside
dsPIC33EPXXXMU806/810/814
PIC24EPXXXGU810/814 architecture provides two
methods by which program space can be accessed
during operation:
• Using table instructions to access individual bytes
• Remapping a portion of the program space into
TABLE 4-70:
FIGURE 4-12:
 2009-2011 Microchip Technology Inc.
Instruction Access
(Code Execution)
TBLRD/TBLWT
(Byte/Word Read/Write)
or words anywhere in the program space
the data space (Program Space Visibility)
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
Access Type
Interfacing Program and Data
Memory Spaces
Program Counter
Table Operations
2: Table operations are not required to be word aligned. Table read operations are permitted in the
dsPIC33EPXXXMU806/810/814
from
alignment of data in the program and data spaces.
configuration memory space.
PROGRAM SPACE ADDRESS CONSTRUCTION
normal
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
User/Configuration Space Select
(2)
(1)
User
User
Configuration
Access
execution,
Space
1/0
0
TBLPAG
8 bits
and
and
Preliminary
the
<23>
0
TBLPAG<7:0>
TBLPAG<7:0>
0xxx xxxx
1xxx xxxx
0xx
Program Counter
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look-ups
from a large table of static data. The application can
only access the least significant word of the program
word.
<22:16>
24 bits
xxxx
23 bits
Program Space Address
xxxx
PC<22:1>
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
16 bits
<15>
EA
xxxx
Data EA<15:0>
Data EA<15:0>
xxxx xxx0
<14:1>
Byte Select
DS70616E-page 123
1/0
0
<0>
0

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