DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 147

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.0
The DMA controller transfers data between peripheral
data
dsPIC33EPXXXMU806/810/814
PIC24EPXXXGU810/814 DMA subsystem uses dual-
ported SRAM memory (DPSRAM) and register
structures that allow the DMA to operate across its
own, independent address and data buses with no
impact on CPU operation. This architecture eliminates
the need for cycle stealing, which halts the CPU when
a higher priority DMA transfer is requested. Both the
CPU and DMA controller can write and read to/from
FIGURE 8-1:
 2009-2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
registers
2: Some registers and associated bits
DIRECT MEMORY ACCESS
(DMA)
of the dsPIC33EPXXXMU806/810/814
and PIC24EPXXXGU810/814 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 22. “Direct Mem-
ory Access (DMA)” (DS70348) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
and
DMA CONTROLLER
PERIPHERAL
data
space
web
SRAM.
site
The
and
Preliminary
DMA
in
addresses within data space without interference, such
as CPU stalls, resulting in maximized, real-time
performance. Alternatively, DMA operation and data
transfer to/from the memory and peripherals are not
impacted by CPU processing. For example, when a
Run-Time Self-Programming (RTSP) operation is
performed, the CPU does not execute any instructions
until RTSP is finished. This condition, however, does
not impact data transfer to/from memory and the
peripherals.
In addition, DMA can access entire data memory space
(SRAM and DPSRAM). The Data Memory Bus Arbiter
is utilized when either the CPU or DMA attempt to
access non-dual-ported SRAM, resulting in potential
DMA or CPU stalls.
The DMA controller supports up to 15 independent
channels. Each channel can be configured for transfers
to or from selected peripherals. Some of the
peripherals supported by the DMA controller include:
• ECAN™
• Data Converter Interface (DCI)
• Analog-to-Digital Converter (ADC)
• Serial Peripheral Interface (SPI)
• UART
• Input Capture
• Output Compare
• Parallel Master Port (PMP)
Refer to
peripherals.
DPSRAM
SRAM
Arbiter
Table 8-1
for a complete list of supported
DS70616E-page 147