DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 259

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 14-2:
 2009-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 8
bit 7
bit 6
bit 5
Note 1:
ICTRIG
R/W-0
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
U-0
—
2:
3:
4:
5:
(2)
The IC32 bit in both the ODD and EVEN IC must be set to enable Cascade mode.
The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
This bit is set by the selected input source (selected by SYNCSEL<4:0> bits). It can be read, set, and
cleared in software.
Do not use the ICx module as its own sync or trigger source.
This option should only be selected as trigger source and not as a synchronization source.
Unimplemented: Read as ‘0’
IC32: 32-bit Timer Mode Select bit (Cascade mode)
1 = ODD IC and EVEN IC form a single 32-bit Input Capture module
0 = Cascade module operation disabled
ICTRIG: Trigger Operation Select bit
1 = Input source used to trigger the input capture timer (Trigger mode)
0 = Input source used to synchronize the input capture timer to a timer of another module
TRIGSTAT: Timer Trigger Status bit
1 = ICxTMR has been triggered and is running
0 = ICxTMR has not been triggered and is being held clear
Unimplemented: Read as ‘0’
TRIGSTAT
R/W/HS-0
(Synchronization mode)
U-0
—
ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
(3)
HS = Set by Hardware
W = Writable bit
U-0
U-0
—
—
R/W-0
U-0
Preliminary
—
(3)
(2)
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
R/W-1
U-0
—
SYNCSEL<4:0>
R/W-1
U-0
—
(1)
R/W-0
U-0
—
DS70616E-page 259
R/W-0
R/W-1
IC32
bit 8
bit 0