A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 85

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-87 • FIFO
Embedded Nonvolatile Memory Block (eNVM)
Table 2-88 • eNVM Block Timing, Worst Commercial Case Conditions: T
Parameter
t
t
Note:
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
FMAXCLKeNVM
FMAXCLKeNVM
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
RCKEF
WCKFF
CKAF
RSTFG
RSTAF
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
*6:1:1:1 indicates 6 cycles for the first access and 1 each for the next three accesses. 5:1:1:1 indicates 5 cycles
for the first access and 1 each for the next three accesses.
For specific junction temperature and voltage supply levels, refer to
Worst Commercial-Case Conditions: T
Timing Characteristics
Electrical Characteristics
Table 2-88
Maximum frequency for clock for the control logic – 6 cycles
(6:1:1:1*)
Maximum frequency for clock for the control logic – 5 cycles
(5:1:1:1*)
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
BLK_B Hold Time
Input Data (DI) Setup Time
Input Data (DI) Hold Time
Clock High to New Data Valid on DO (flow-through)
Clock High to New Data Valid on DO (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B Low to Empty/Full Flag Valid
RESET_B Low to Almost Empty/Full Flag Valid
RESET_B Low to Data Out Low on DO (flow-through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle Time
Maximum Frequency for FIFO
describes the eNVM maximum performance.
Description
Description
J
= 85°C, VCC = 1.425 V
R e v i s i o n 6
SmartFusion Intelligent Mixed Signal FPGAs
Table 2-7 on page 2-9
J
= 85°C, VCC = 1.425 V
100
–1
80
A2F200
Std.
80
80
1.40
0.02
0.00
0.19
0.00
2.39
1.74
0.94
0.94
0.29
1.52
3.28
0.19
0.91
1.66
6.29
1.72
6.22
0.22
305
–1
100
–1
50
for derating values.
A2F500
1.68
0.02
0.19
0.00
0.22
0.00
2.87
2.09
1.12
1.12
3.28
Std.
1.09
1.99
7.54
2.06
7.47
0.35
1.83
0.22
305
Std.
50
80
Units
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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