A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 185

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
Revision 4
(September
2010)
Revision 3
(September
2010)
Table 2-8 • Quiescent Supply Current Characteristics
moved to a column of its own with new values. VCCENVM was added to the table.
Standby mode for VJTAG and VPP was changed from 0 V to N/A. "Disable" was
changed to "Off "in the eNVM column. The column for RCOSC was deleted.
The
VCCROSC.
The
with on-chip 1.5 V regulator" and "external 1.5 V is allowed" (SAR 27663).
The CS288 package was added to the
27101),
(SAR 27044). The number of direct analog inputs for the FG256 package in A2F060
was changed from 8 to 6.
Two notes were added to the
limitations for features of the A2F500 device:
Table cells were merged in rows containing the same values for easier reading (SAR
24748).
The security feature option was added to the
In
operating range was changed from "2.97 to 3.63" to "2.7 to 3.63" (SAR 25246).
Recommended operating range was changed to "3.15 to 3.45" for the following
voltages:
Two notes were added to the table (SAR 27109):
1. The following 3.3 V supplies should be connected together while following proper noise
2. The following 1.5 V supplies should be connected together while following proper noise
In
was corrected to change "32 Hz" to "32 KHz" (SAR 27110).
The
Table 2-8 • Quiescent Supply Current Characteristics
on/off entries to voltages. Note 5 was added, stating that "on" means proper voltage is
applied. The values of 6 µA and 16 µA were removed for IDC1 and IDC2 for 3.3 V. A
note was added for IDC1 and IDC2: "Power mode and Sleep mode are consuming
higher current than expected in the current version of silicon. These specifications will
be updated when new version of the silicon is available" (SAR 27926).
The
Two PLLs are available in CS288 and FG484 (one PLL in FG256).
[ADCs, DACs, SCBs, comparators, current monitors, and bipolar high voltage
monitors are] Available on FG484 only. FG256 and CS288 packages offer the same
programmable analog capabilities as A2F200.
Table 2-3 • Recommended Operating
Table 2-3 • Recommended Operating
filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL,
and VCCLPXTAL.
filtering practices: VCC, VCC15A, and VCC15ADCx.
"I/Os and Operating Voltage" section
VCC33A
VCC33ADCx
VCC33AP
VCC33SDDx
VCCMAINXTAL
VCCLPXTAL
"Power Supply Sequencing Requirement" section
"Power-Down and Sleep Mode Implementation" section
"Power-Down and Sleep Mode Implementation" section
"Product Ordering Codes"
"SmartFusion Family Product Table"
table, and
Changes
R e v i s i o n 6
"Package I/Os: MSS + FPGA I/Os" table
was revised to list "single 3.3 V power supply
Conditions, the description for VCCLPXTAL
Conditions, the VDDBAT recommended
"Product Ordering Codes"
"Temperature Grade Offerings" table
SmartFusion Intelligent Mixed Signal FPGAs
is new (SAR 27178).
was revised. VCCRCOSC was
was revised to change most
is new (SAR 27178).
was revised to include
table.
indicating
(SAR
III, VI,
Page
2-10
2-11
2-10
2-11
2-3
2-3
2-4
VI
II
I
VI
6 -3