A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 35

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial
Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
2.5 V LVCMOS 12 mA High –0.3
1.8 V LVCMOS 12 mA High –0.3
1.5 V LVCMOS 12 mA High –0.3
3.3 V PCI
3.3 V PCI-X
Notes:
1. Currents are measured at 85°C junction temperature.
2. Output slew rate can be extracted by the IBIS Models.
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
2.5 V LVCMOS 8 mA
1.8 V LVCMOS 4 mA
1.5 V LVCMOS 2 mA
Notes:
1. Currents are measured at 85°C junction temperature.
2. Output slew rate can be extracted by the IBIS Models.
Conditions—Software Default Settings
Applicable to FPGA I/O Banks
Conditions—Software Default Settings
Applicable to MSS I/O Banks
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Strgth.
Strgth.
12 mA High –0.3
Drive
Drive
8 mA
Slew
Rate
Slew
Rate
High –0.3
High –0.3
High –0.3
High –0.3
Min.
Min.
V
V
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VIL
VIL
0.35 *
0.35 *
0.35*
0.35*
Max.
Max.
0.8
0.7
0.8
0.7
V
V
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
Per PCI-X specifications
Per PCI specifications
0.65*
0.65*
R e v i s i o n 6
0.65*
0.65*
Min.
Min.
1.7
1.7
V
V
2
2
VIH
VIH
Max.
Max.
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
V
SmartFusion Intelligent Mixed Signal FPGAs
VCCxxxxIOBx
VCCxxxxIOBx
0.25 *
Max.
0.25*
VOL
Max.
VOL
0.45
0.45
0.4
0.7
0.4
0.7
V
V
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
– 0.45
– 0.45
0.75*
0.75*
VOH
VOH
Min.
Min.
2.4
1.7
2.4
1.7
V
V
I
I
mA mA
mA mA
OL
OL
12
12
12
12
8
4
2
8
1
1
I
I
OH
OH
2- 23
12
12
12
12
8
4
2
8
1
1