MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 95

IC MPU 66MHZ COLDFIRE 196-MAPBGA

MCF5272CVM66

Manufacturer Part Number
MCF5272CVM66
Description
IC MPU 66MHZ COLDFIRE 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5272CVM66

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Cpu Speed
66MHz
Embedded Interface Type
UART, QSPI, USB, TDM
Digital Ic Case Style
BGA
No. Of Pins
196
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant

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ColdFire processors inhibit sampling for interrupts during the first instruction of all exception handlers.
This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level
contained in the status register.
2.8.1
The exception stack frame is shown in
contains the 16-bit format/vector word (F/V) and the 16-bit status register. The second longword contains
the 32-bit program counter address.
The 16-bit format/vector word contains three unique fields:
Freescale Semiconductor
+ 0x04
A7→
1
Format field—This 4-bit field at the top of the system stack is always written with a value of
{4,5,6,7} by the processor indicating a 2-longword frame format. See
records any longword misalignment of the stack pointer that may have existed when the exception
occurred.
Fault status field—The 4-bit field, FS[3–0], at the top of the system stack is defined for access and
address errors along with interrupted debug service routines. See
Numbers
The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC
of the instruction that immediately follows the instruction that caused the fault.
64–255
Vector
62–63
Exception Stack Frame Definition
61
31
Format
Original A7 at Time of
Exception, Bits 1–0
MCF5272 ColdFire
Vector Offset
0F8–0FC
100–3FC
28
Table 2-18. Exception Vector Assignments (continued)
(Hex)
0F4
00
01
10
11
27
FS[3–2]
Figure 2-10. Exception Stack Frame Form
26
Table 2-19. Format Field Encoding
25
®
Figure
Vector[7–0]
Program Counter
Integrated Microprocessor User’s Manual, Rev. 3
Stacked
Program Counter [31–0]
A7 at First Instruction of
Fault
Next
2-10. The first longword of the exception stack frame
18
Original A[7–10]
Original A[7–11]
Original A[7–8]
Original A[7–9]
17
FS[1–0]
Handler
1
16
Unsupported instruction
Reserved
User-defined interrupts
15
Format Field Bits
Table
Assignment
Status Register
31–28
Table
0100
0101
0110
0111
2-20.
2-19. This field
ColdFire Core
0
2-27

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