MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 71

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

For register-to-memory operations, the stage functions (DS/OC, AG/EX) are effectively performed
simultaneously allowing single-cycle execution. For read-modify-write instructions, the pipeline
effectively combines a memory-to-register operation with a store operation.
2.1.1.2.1
On Version 2 ColdFire implementations, only some illegal opcodes (0x0000 and 0x4AFC) are decoded
and generate an illegal instruction exception. Additionally, attempting to execute an illegal line A or line F
opcode generates unique exception types. If any other unsupported opcode is executed, the resulting
operation is undefined.
2.1.1.2.2
The MAC is an optional unit in Version 2 that provides hardware support for a limited set of digital signal
processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in
the ColdFire microprocessor family. The MAC features a three-stage execution pipeline, optimized for 16
x 16 multiplies. It is tightly coupled to the OEP, which can issue a 16 x 16 multiply with a 32-bit
accumulation plus fetch a 32-bit operand in a single cycle. A 32 x 32 multiply with a 32-bit accumulation
requires three cycles before the next instruction can be issued.
Figure 2-2
unsigned integers plus signed, fixed-point fractional input operands.
The MAC provides functionality in the following three related areas, which are described in detail in
Chapter 3, “Hardware Multiply/Accumulate (MAC)
Freescale Semiconductor
•
•
•
Signed and unsigned integer multiplies
Multiply-accumulate operations with signed and unsigned fractional operands
Miscellaneous register operations
shows basic functionality of the MAC. A full set of instructions are provided for signed and
Illegal Opcode Handling
Hardware Multiply/Accumulate (MAC) Unit
Figure 2-2. ColdFire Multiply-Accumulate Functionality Diagram
MCF5272 ColdFire
®
Operand Y
Integrated Microprocessor User’s Manual, Rev. 3
Accumulator
Shift 0,1,-1
+/-
X
Unit.”
Operand X
ColdFire Core
2-3