MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 278

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus (USB)
12.3.2.14 USB Endpoint 1–7 Control Register (EPnCTL)
Figure 12-17
Table 12-13
12-20
15–8
Bits
5–4
3–2
7
6
Reset
Reset
Field
Field CRC_ERR ISO_MODE
Addr
R/W
R/W
ISO_MODE Isochronous transfer mode. This bit must be set when the endpoint is configured for isochronous
CRC_ERR
FIFO_LVL
lists the field descriptions for the USB endpoint 1–7 control register.
Name
shows the USB endpoint 1–7 control register.
—
—
15
7
MCF5272 ColdFire
Reserved, should be cleared.
CRC error generation enable. Enables CRC error generation for debug and test purposes. To use this
feature, the DEBUG bit must be set. Enabling this bit causes a CRC error on the next non-zero-length
data packet transmitted. The CRC_ERR bit must be set again in order to generate another CRC error.
This bit is only valid for IN endpoints. This command bit is write only and always returns 0 when read.
0 Default Value
1 CRC error generation if DEBUG = 1
mode.
0 Non-isochronous transfer mode
1 Isochronous transfer mode
Reserved, should be cleared.
Endpoint n FIFO level for interrupt. This field selects the FIFO level to generate a FIFO_LVL interrupt.
The FIFO_LVL interrupt is generated when the FIFO fills above (OUT) or falls below (IN) the selected
level.
00 FIFO
01 FIFO
10 FIFO
11 FIFO emptyFIFO full
Figure 12-17. USB Endpoint 1-7 Control Register (EP
IN FIFOOUT FIFO
MBAR + 0x1052, 0x1056, 0x105A, 0x105E, 0x1062, 0x1066, 0x106A
6
25%
50%
75%
Table 12-13. EP
emptyFIFO
emptyFIFO
emptyFIFO
®
5
Integrated Microprocessor User’s Manual, Rev. 3
25%
50%
75%
—
full
full
full
n
CTL Field Descriptions
4
0000_0000
0000_0004
R/W
R/W
—
Description
3
FIFO_LVL
2
n
CTL)
IN_DONE
1
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