MCF5282CVM66 Freescale Semiconductor, MCF5282CVM66 Datasheet - Page 61

• Manufacturer Part Number: MCF5282CVM66
• Description: IC MPU 512K 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 2-4
see the ColdFire Family Programmer’s Reference Manual.
2.3.3
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
differ from the M68000 family because they include:
All ColdFire processors use an instruction restart exception model. However, Version 2 ColdFire
processors require more software support to recover from certain access errors. See
“Access Error
Exception processing includes all actions from fault condition detection to the initiation of fetch for first
handler instruction. Exception processing is comprised of four major steps:
Freescale Semiconductor
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1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
2. The processor determines the exception vector number. For all faults except interrupts, the
Move from USP USP → Destination register
A simplified exception vector table
Reduced relocation capabilities using the vector-base register
A single exception stack frame format
Use of separate system stack pointers for user and supervisor modes.
bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to
be cleared and the interrupt priority mask to set to current interrupt request level.
processor performs this calculation based on exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller. The IACK cycle is mapped to special locations within the interrupt
controller’s address space with the interrupt level encoded in the address.
Move to USP
Instruction
BYTEREV
STLDSR
BITREV
summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details
FF1
Exception Processing Overview
Exception” for details.
The contents of the destination data register are bit-reversed; new Dn[31] equals old Dn[0], new
Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31].
The contents of the destination data register are byte-reversed; new Dn[31:24] equals old
Dn[7:0],..., new Dn[7:0] equals old Dn[31:24].
The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending
with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.
Source register → USP
Pushes the contents of the status register onto the stack and then reloads the status register
with the immediate data value.
Table 2-4. Instruction Enhancements over Revision ISA_A
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Description
Section 2.3.4.1,
ColdFire Core
2-15