MCF5282CVM66 Freescale Semiconductor, MCF5282CVM66 Datasheet - Page 238

• Manufacturer Part Number: MCF5282CVM66
• Description: IC MPU 512K 66MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

External Interface Module (EIM)
13.5
Because operands can reside at any byte boundary, unlike opcodes, they are allowed to be misaligned. A
byte operand is properly aligned at any address, a word operand is misaligned at an odd address, and a
longword is misaligned at an address not a multiple of four. Although the processor enforces no alignment
restrictions for data operands (including program counter (PC) relative data addressing), additional bus
cycles are required for misaligned operands.
Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch
a misaligned instruction word causes an address error exception.
The processor converts misaligned, cache-inhibited operand accesses to multiple aligned accesses.
Figure 13-19
example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1. The slave device supplies the byte and
acknowledges the data transfer. When the processor starts the second cycle, SIZ[1:0] specify a word
transfer with a byte offset of 0x2. The next two bytes are transferred in this cycle. In the third cycle, byte
3 is transferred. The byte offset is now 0x0, the port supplies the final byte, and the operation is complete.
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the
cache. The example in
the transfer takes only two bus cycles.
13-14
CLKOUT
R/W, TIP
OE, BSn
SIZ[1:0]
D[31:0]
A[31:0]
CSn
TS
TA
Misaligned Operands
Transfer 1
Transfer 2
Transfer 3
shows the transfer of a longword operand from a byte address to a 32-bit port. In this
Figure 13-19. Example of a Misaligned Longword Transfer (32-Bit Port)
31
S0
Figure 13-20
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
S1
Byte 3
—
—
A[3:2] = 00
S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5
Basic
Write
Line
Figure 13-18. Line Write Burst-Inhibited
24 23
differs from that in
Byte 0
—
—
A[3:2] = 01
16 15
Fast
Write
Figure 13-19
Byte 1
—
—
A[3:2] = 10
Longword
8 7
Fast
in that the operand is word-sized and
Write
Byte 2
—
—
A[3:2] = 11
0
Fast
Freescale Semiconductor
Write
A[2:0]
001
010
100