MC9S12XDT256MAG Freescale Semiconductor, MC9S12XDT256MAG Datasheet - Page 114

• Manufacturer Part Number: MC9S12XDT256MAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted
synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven
low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
114
Sampled RESET Pin
after release)
(64 cycles
1
1
1
0
SYSCLK
RESET
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic 1 within 64 SYSCLK cycles after the low drive is released.
Reset Pending
Clock Monitor
X
0
1
0
Possibly
SYSCLK
not
running
Table 2-15. Reset Vector Selection
MC9S12XDP512 Data Sheet, Rev. 2.21
CRG drives RESET pin low
) (
Figure 2-25. RESET Timing
Reset Pending
COP
With n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
X
X
0
1
128 + n cycles
NOTE
) (
)
(
POR / LVR / Illegal Address Reset / External Reset
POR / LVR / Illegal Address Reset / External Reset
RESET pin
released
64 cycles
)
(
with rise of RESET pin
Clock Monitor Reset
Vector Fetch
Possibly
RESET
driven low
externally
COP Reset
)
(
Freescale Semiconductor