PIC18F6410-I/PT Microchip Technology, PIC18F6410-I/PT Datasheet - Page 82

• Manufacturer Part Number: PIC18F6410-I/PT
• Description: IC PIC MCU FLASH 8KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6410-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
TABLE 6-3:
DS39635C-page 82
SPBRGH1
BAUDCON1
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset
These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See
INTOSC
The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
STKFUL and STKUNF bits are cleared by user software or by a POR.
EUSART1 Baud Rate Generator High Byte
AUSART2 Baud Rate Generator
AUSART2 Receive Register
AUSART2 Transmit Register
ABDOVF
CSRC
SPEN
Bit 7
REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
Modes”.
RCIDL
Bit 6
TX9
RX9
RXDTP
SREN
TXEN
(BOR)”.
Bit 5
TXCKP
SYNC
CREN
Bit 4
ADDEN
BRG16
Bit 3
—
BRGH
FERR
Bit 2
—
OERR
TRMT
WUE
Bit 1
 2010 Microchip Technology Inc.
ABDEN
RX9D
TX9D
Bit 0
0000 0000
0100 0-00
0000 0000
0000 0000
xxxx xxxx
0000 -010
0000 000x
POR, BOR
Section 3.6.4 “PLL in
Value on
on page:
Details
66, 221
66, 220
66, 234
66, 248
66, 246
66, 242
66, 243