PIC18F6410-I/PT Microchip Technology, PIC18F6410-I/PT Datasheet - Page 248

• Manufacturer Part Number: PIC18F6410-I/PT
• Description: IC PIC MCU FLASH 8KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6410-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
19.2.2
The receiver block diagram is shown in
The data is received on the RX2 pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
in RS-232 systems.
To set up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If using interrupts, ensure that the GIE and PEIE
FIGURE 19-4:
DS39635C-page 248
Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH bit, as required,
to achieve the desired baud rate.
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If interrupts are desired, set enable bit, RC2IE.
If 9-bit reception is desired, set bit, RX9.
Enable the reception by setting bit, CREN.
Flag bit, RC2IF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RC2IE, was set.
Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG2 register.
If any error occurred, clear the error by clearing
enable bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
AUSART ASYNCHRONOUS
RECEIVER
RX2
OSC
. This mode would typically be used
AUSART RECEIVE BLOCK DIAGRAM
and Control
Pin Buffer
Baud Rate Generator
x64 Baud Rate CLK
SPEN
SPBRG2
Figure
19-4.
Recovery
Interrupt
 64
 16
 4
Data
or
or
CREN
19.2.3
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
RX9
Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH and BRG16
bits, as required, to achieve the desired baud
rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RC2IP
bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RC2IF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RC2IE and GIE bits are set.
Read the RCSTA2 register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
Read RCREG2 to determine if the device is
being addressed.
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
Stop
MSb
RC2IF
RC2IE
RX9D
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
(8)
OERR
7
RSR Register
RCREG2 Register

 2010 Microchip Technology Inc.
8
Data Bus
1
FERR
0
LSb
Start
FIFO