PIC18F6410-I/PT Microchip Technology, PIC18F6410-I/PT Datasheet
PIC18F6410-I/PT
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... PIC18F6310/6410/8310/8410 64/80-Pin Flash Microcontrollers 2004 Microchip Technology Inc. Data Sheet with nanoWatt Technology Preliminary DS39635A ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Address capability Mbytes • 16-bit/8-bit interface Program Memory (On-Board/External) Device Flash # Single-Word (bytes) Instructions PIC18F6310 8K/0 4096/0 PIC18F6410 16K/0 8192/0 PIC18F8310 8K/2M 4096/1M PIC18F8410 16K/2M 8192/1M 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Peripheral Highlights: • High current sink/source 25 mA/25 mA • Four external interrupts • ...
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... RG0/CCP3 3 RG1/TX2/CK2 4 RG2/RX2/DT2 5 RG3 6 RG5/MCLR RG4 RF7/SS 11 RF6/AN11 12 RF5/AN10/CV REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT 16 Note 1: RE7 is the alternate pin for CCP2 multiplexing DS39635A-page PIC18F6310 PIC18F6410 Preliminary 50 49 RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 RB7/KBI3/PGD 37 RC5/SDO 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1 ...
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... RG2/RX2/DT2 7 RG3 8 RG5/MCLR RG4 RF7/SS 13 RF6/AN11 14 RF5/AN10/CV REF 15 RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 RH7 19 RH6 Note 1: RE7 is the alternate pin for CCP2 multiplexing 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 PIC18F8310 PIC18F8410 Preliminary RJ2/WRL 60 RJ3/WRH 59 RB0/INT0 58 RB1/INT1 57 RB2/INT2 56 (1) RB3/INT3/CCP2 55 RB4/KBI0 54 RB5/KBI1 53 RB6/KBI2/PGC OSC2/CLKO/RA6 ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 387 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 387 Index .................................................................................................................................................................................................. 389 On-Line Support................................................................................................................................................................................. 399 Systems Information and Upgrade Hot Line ...................................................................................................................................... 399 Reader Response .............................................................................................................................................................................. 400 PIC18F6310/6410/8310/8410 Product Identification System ............................................................................................................ 401 DS39635A-page 4 Preliminary 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Preliminary DS39635A-page 5 ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 6 Preliminary 2004 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F6310 • PIC18LF6310 • PIC18F6410 • PIC18LF6410 • PIC18F8310 • PIC18LF8310 • PIC18F8410 • PIC18LF8410 This family offers the advantages of all PIC18 microcontrollers – namely, high performance at an economical price. In addition to ...
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... DS39635A-page 8 1.3 Details on Individual Family Members Devices in the PIC18F6310/6410/8310/8410 family are available in 64-pin (PIC18F6310/8310) and 80-pin (PIC18F6410/8410) packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2, respectively. The devices are differentiated from each other in three ways: 1. ...
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... Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) POR, BOR, RESET Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 PIC18F6310 PIC18F6410 DC – 40 MHz DC – 40 MHz 8K 16K 4096 8192 768 768 No No ...
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... RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 PORTD RD7/PSP7:RD0/PSP0 PORTE 8 RE0/RD RE1/WR RE2/CS RE3 RE4 RE5 RE6 (1) RE7/CCP2 PORTF RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CV REF RF6/AN11 RF7/SS PORTG RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3 RG4 (2) RG5 /MCLR/V PP 2004 Microchip Technology Inc. ...
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... RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Data Latch 8 ...
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... In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2004 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2004 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... Parallel Slave Port data. I/O ST Digital I/O. I/O TTL Parallel Slave Port data. I/O ST Digital I/O. I/O TTL Parallel Slave Port data. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2004 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O ...
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... Analog input 10. O Analog Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog input 11. I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2004 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2004 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2004 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... External memory address/data 6. I/O TTL Parallel Slave Port data. I/O ST Digital I/O. I/O TTL External memory address/data 7. I/O TTL Parallel Slave Port data. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2004 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... Analog input 10. O Analog Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog input 11. I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2004 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for CCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTG is a bidirectional I/O port ...
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... Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. P — Ground reference for analog modules. P — Positive supply for analog modules. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary Description ) DD 2004 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... Clock from Ext. System Preliminary EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX RA6 I/O (OSC2) 2004 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit clock the device up to its highest rated frequency from a crystal oscillator ...
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... OSTUNE register. This has no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made and in some cases, how large a change is needed. Three examples follow, but other techniques may be used. Preliminary 2004 Microchip Technology Inc. ...
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... Minimum frequency Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2.6.5.3 Compensating with the Timers A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i ...
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... MHz 101 1 MHz 100 500 kHz 011 250 kHz FOSC3:FOSC0 010 125 kHz 001 31 kHz 1 000 0 OSCTUNE<7> Preliminary 2004 Microchip Technology Inc. Peripherals CPU IDLEN Clock Control OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Start-up ...
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... INTRC is providing the clock, or the internal oscillator block has just started and is not yet stable. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... R = Readable bit -n = Value at POR DS39635A-page 36 (1) R/W-0 R/W-0 R R-0 IRCF1 IRCF0 OSTS IOFS (2) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown 2004 Microchip Technology Inc. ...
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... LP, XT and HS Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 38 Preliminary 2004 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power managed modes. They are: • ...
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... When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Preliminary 2004 Microchip Technology Inc. ...
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... FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 T1OSI OSC1 T PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed Note 1024 OST OSC PLL 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 n-1 n Clock Transition OST (1) PLL ( n-1 Clock ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition OST (1) (1) T PLL 1 2 n-1 n Clock Transition PC OSTS bit Set = 2 ms (approx). These intervals are not shown to scale. Preliminary 2004 Microchip Technology Inc. ...
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... Wake Event Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 3.4 Idle Modes in the The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to ® ...
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... This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-8 CSD PC Preliminary is CSD 2004 Microchip Technology Inc. ...
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... In such situations, initial oscillator operation is far from stable and unpredictable operation may result. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled, but the periph- erals continue to be clocked from the internal oscillator block using the INTOSC multiplexer ...
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... Oscillator modes). However, a fixed delay of interval T , following the wake event, is still required when CSD leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. Preliminary 2004 Microchip Technology Inc. ...
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... Section 3.4 “Idle Modes”). 3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies the Oscillator Start-up Timer (parameter 32). t OST also designated PLL 5: Execution continues during T 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Clock Source Exit Delay after Wake-up LP, XT, HS HSPLL T CSD (1) EC, RC, INTRC (3) ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 48 Preliminary 2004 Microchip Technology Inc. ...
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... INTRC 11-bit Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1) ...
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... POR was set to ‘1’ by software immediately after POR). DS39635A-page 50 (1) U-0 R/W-1 R-1 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2004 Microchip Technology Inc. ...
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... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 FIGURE 4- ...
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... BOR is disabled; must be enabled by reprogramming the configuration bits. BOR is enabled in software; operation controlled by SBOREN. BOR is enabled in hardware and active during the Run and Idle modes, disabled during Sleep mode. BOR is enabled in hardware; must be disabled by reprogramming the configuration bits. Preliminary 2004 Microchip Technology Inc. ...
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... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly different from other oscillator modes ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39635A-page 54 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary 2004 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 , V RISE > PWRT T OST T PWRT ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( Preliminary STKPTR Register POR BOR STKFUL STKUNF 2004 Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 MCLR Resets Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 MCLR Resets Power-on Reset, ...
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... PIC18FX410 PC<20:0> CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 31 Reset Vector High Priority Interrupt Vector 0008h Low Priority Interrupt Vector On-Chip Program Memory Read ‘0’ Preliminary The PIC18F6410 and memory maps for the 21 • • • 0000h 0018h 3FFFh 4000h 1FFFFFh ...
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... Flash memory. Attempts to read above the physical limit of the on-chip Flash (3FFFh) causes a read of all ‘0’s (a NOP instruction). The Microcontroller mode is also the only operating mode available to PIC18F6310 and PIC18F6410 devices. REGISTER 5-1: CONFIG3L: CONFIGURATION BYTE REGISTER 3 LOW R/P-1 R/P-1 ...
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... Table Read Mode From Microcontroller Yes Extended Yes Microcontroller Microprocessor No Access No Access Microprocessor Yes w/ Boot Block 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Extended Microcontroller Mode 000000h (Top of Memory) (Top of Memory 1FFFFFh Microprocessor with Boot Block Mode 000000h 0007FFh 000800h (No (Top of Memory 1FFFFFh ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 Preliminary to by the STKPTR register can return these values to Stack Pointer STKPTR<4:0> 00010 2004 Microchip Technology Inc. ...
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... Note 1: Bit 7 and bit 6 are cleared by user software POR. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Table Latch (TABLAT) register contains the data that is read from the program memory. Data is transferred from program memory one byte at a time. Table read operation Section 6.1 “Table Reads and Table Writes”. Preliminary 2004 Microchip Technology Inc. is discussed further in ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 2004 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 5.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh 2004 Microchip Technology Inc. ...
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... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Data Memory 000h 7 ...
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... RCSTA2 (2) LATB F6Ah — (2) LATA F69h — (3) (2) PORTJ F68h — (3) (2) PORTH F67h — (2) PORTG F66h — (2) PORTF F65h — (2) PORTE F64h — (2) PORTD F63h — (2) PORTC F62h — (2) PORTB F61h — (2) PORTA F60h — 2004 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: STKFUL and STKUNF bits are cleared by user software POR. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 4 Bit 3 ...
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... CCP2M0 59, 159 --00 0000 59, 160 xxxx xxxx 59, 160 0000 0000 CCP3M0 59, 159 --00 0000 CVR0 59, 261 0000 0000 CM0 59, 255 0000 0111 59, 157 0000 0000 59, 157 0000 0000 TMR3ON 59, 155 0000 0000 — 59, 141 0000 ---- 2004 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: STKFUL and STKUNF bits are cleared by user software POR. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 4 Bit 3 ...
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... TRMT CREN ADDEN FERR OERR Preliminary Value on Details Bit 0 POR, BOR on page: 60, 213 0000 0000 ABDEN 60, 212 01-0 0-00 60, 234 0000 0000 60, 238 0000 0000 60, 236 xxxx xxxx TX9D 60, 232 0000 -010 RX9D 60, 233 0000 000x 2004 Microchip Technology Inc. ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the Status register, because these instructions do not affect the bits in the Status register ...
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... EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE Preliminary 2004 Microchip Technology Inc. ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ; YES, continue ...
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... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. ...
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... Similarly, operations by indirect addressing are gener- ally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. Preliminary 2004 Microchip Technology Inc. ...
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... This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When using the extended instruction set, this addressing mode requires the following: • ...
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... F00h Bank 15 F40h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F40h SFRs FFFh Data Memory Preliminary 2004 Microchip Technology Inc. 00h 60h Valid Range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F00h BSR. F60h FFFh 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. Any indirect or ...
Page 86
... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 84 Preliminary 2004 Microchip Technology Inc. ...
Page 87
... Note 1: Table Pointer register points to a byte in the program memory space. 2: Data is actually written to the memory location by the memory write algorithm. See Section 6.4 “Writing to Program Memory Space (PIC18F8310/8410 only)” for more information. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 The program memory space is 16 bits wide, while the data RAM space is 8 bits wide ...
Page 88
... A typical method for reading data from program memory is shown in Example 6-1. Program Memory Space (Odd Byte Address) TBLPTR = xxxxx1 TBLRD Preliminary TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Operation on Table Pointer TBLPTR = xxxxx0 TABLAT Read Register 2004 Microchip Technology Inc. ...
Page 89
... The best place for timing and instruction sequence requirements is the data sheet of the memory device in question. For additional information on algorithm design for the external 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 ; Load TBLPTR with the base ; address of the word ...
Page 90
... Code Protection See Section 23.5 “Program Verification and Code Protection” for details on code protection of Flash program memory. Bit 5 Bit 4 Bit 3 Bit 2 bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Preliminary Reset Bit 1 Bit 0 Values on Page 2004 Microchip Technology Inc. ...
Page 91
... Note: The external memory interface is not implemented on PIC18F6310 PIC18F6410 (64-pin) devices. The external memory interface allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE and PORTH) are ...
Page 92
... Microprocessor with Boot Block mode or Extended Microcontroller mode, the control signals will NOT be active. They will state where the AD<15:0> and A<19:16> are tri-state; the CE, OE, WRH, WRL, UB and LB signals are ‘1’; ALE and BA0 are ‘0’. Preliminary 2004 Microchip Technology Inc. ...
Page 93
... OE WRH WRL Note 1: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 at any time that the microcontroller accesses external memory, whether reading or writing inactive (asserted high) whenever the device is in Sleep mode. ...
Page 94
... WORD WRITE MODE Figure 7-2 shows an example of 16-bit Word Write mode for PIC18F6410 devices. This mode is used for word-wide memories, which includes some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories ...
Page 95
... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. 2: Demultiplexing is only required when multiple memory devices are accessed. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 96
... TBLRD Cycle 0Ch CF33h Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 2 Preliminary 0Ch 9256h ‘1’ ‘1’ ‘0’ Wait 9256h Opcode Fetch ADDLW 55h from 000104h MOVLW 2004 Microchip Technology Inc. ...
Page 97
... EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE A<19:16> 00h AD<15:0> 3AAAh 0003h CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Preliminary Bus Inactive DS39635A-page 95 ...
Page 98
... PIC18F6310/6410/8310/8410 7.3 8-Bit Mode The external memory interface implemented in PIC18F6410 devices operates only in Multiplexed 8-bit mode; data shares the 8 Least Significant bits of the address bus. Figure 7-1 shows an example of 8-bit Multiplexed mode for PIC18F8310/8410 devices. This mode is used for a single 8-bit memory connected for 16-bit operation ...
Page 99
... FIGURE 7-9: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE A<19:16> AD<15:8> AD<7:0> CE ALE OE Opcode Fetch Memory TBLRD * Cycle from 000100h Instruction INST(PC – 2) Execution 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 0Eh 55h 33h Table Read of 92h from 199E67h TBLRD Cycle 2 ...
Page 100
... AD<15:8> 3Ah AD<7:0> AAh 00h 03h CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution DS39635A-page 00h 3Ah 0Eh 55h ABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Preliminary Bus Inactive 2004 Microchip Technology Inc. ...
Page 101
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...
Page 102
... ARG2H, W SUBWFB RES3 ; CONT_CODE : Preliminary SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; 2004 Microchip Technology Inc. ...
Page 103
... Individual interrupts can be disabled through their corresponding enable bits. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are devices ...
Page 104
... GIEL/PEIE IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Preliminary 2004 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...
Page 105
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 106
... DS39635A-page 104 R/W-1 R/W-1 R/W-1 INTEDG1 INTEDG2 INTEDG3 TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 107
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 ...
Page 108
... R-0 R/W-0 R/W-0 RC1IF TX1IF SSPIF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary Enable bit, GIE should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 109
... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 U-0 R/W-0 — — BCLIF W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 110
... Value at POR DS39635A-page 108 U-0 R-0 R-0 U-0 — RC2IF TX2IF — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 U-0 R/W-0 — — CCP3IF bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 111
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 ADIE RC1IE TX1IE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 112
... R = Readable bit -n = Value at POR DS39635A-page 110 U-0 U-0 R/W-0 R/W-0 — — BCLIE HLVDIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary 2004 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
Page 113
... Enabled 0 = Disabled bit 3-1 Unimplemented: Read as ‘0’ bit 0 CCP3IE: CCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 R-0 R-0 U-0 — RC2IE TX2IE — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 114
... R = Readable bit -n = Value at POR DS39635A-page 112 R/W-1 R/W-1 R/W-1 R/W-1 RC1IP TX1IP SSPIP CCP1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 115
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 U-0 R/W-1 — — BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 116
... Value at POR DS39635A-page 114 U-0 R-0 R-0 U-0 — RC2IP TX2IP — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 U-0 R/W-1 — — CCP3IP bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 117
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 R/W-1 R-1 — Writable bit U = Unimplemented bit, read as ‘ ...
Page 118
... Example 9-1 saves and restores the WREG, Status and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary 2004 Microchip Technology Inc. ...
Page 119
... Port Note 1: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 120
... PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. I ANA Main oscillator input connection. I ANA Main clock input connection. O DIG LATA<7> data output. Disabled in external oscillator modes. I TTL PORTA<7> data input. Disabled in external oscillator modes. Preliminary Description /4) in all oscillator modes except OSC 2004 Microchip Technology Inc. ...
Page 121
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 ...
Page 122
... Microcontroller mode. If the device is in Microcontroller mode, the alternate assignment for CCP2 is RE7. As with other CCP2 con- figurations, the user must ensure that the TRISB<3> bit is set appropriately for the intended operation. Preliminary 2004 Microchip Technology Inc. ...
Page 123
... Alternate assignment for CCP2 when the CCP2MX configuration bit is cleared (Microprocessor, Extended Microcontroller and Microcontroller with Boot Block modes, 80-pin devices only). Default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD operations are enabled. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O ...
Page 124
... Legend: Shaded cells are not used by PORTB. DS39635A-page 122 Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF INT3IE INT2IE INT1IE INT3IF Preliminary Reset Bit 1 Bit 0 Values on Page RB1 RB0 INT0IF RBIF 57 INT3IP RBIP 57 INT2IF INT1IF 57 2004 Microchip Technology Inc. ...
Page 125
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Note Power-on Reset, these pins are configured as digital inputs ...
Page 126
... I ST PORTC<7> data input Asynchronous serial receive data input (EUSART module) O DIG Synchronous serial data output (EUSART module); takes priority over port data Synchronous serial data input (EUSART module). User must configure as an input. Preliminary Description 2004 Microchip Technology Inc. ...
Page 127
... SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC Data Output Register TRISC PORTC Data Direction Register Legend: Shaded cells are not used by PORTC. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Preliminary Reset ...
Page 128
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs Preliminary 2004 Microchip Technology Inc. ...
Page 129
... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PSP I/O. 2: Implemented on 80-pin devices only. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type ...
Page 130
... External memory interface, data bit 7 input O DIG PSP read data output (LATD<7>); takes priority over port data. I TTL PSP write data input. Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 Preliminary Description (1) . (1) . Reset Bit 1 Bit 0 Values on Page RD1 RD0 2004 Microchip Technology Inc. ...
Page 131
... When the interface is enabled (80-pin devices only), PORTE is the high-order byte of the multiplexed address/data bus (AD15:AD8). The TRISE bits are also overridden. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the Parallel Slave Port is active on PORTD, three of the PORTE pins (RE0/AD8/RD, RE1/AD9/WR and RE2/AD10/CS) are configured as digital control inputs for the port ...
Page 132
... CCP2 compare output and CCP2 PWM output; takes priority over port data CCP2 capture input. O DIG External memory interface, address/data bit 15 output I TTL External memory interface, data bit 15 input Preliminary Description (2) . (2) . (2) . (2) . (2) . (2) . (2) . (2) . (2) . (2) . (2) . (2) . (2) . (2) . (2) . (2) . 2004 Microchip Technology Inc. ...
Page 133
... Bit 7 Bit 6 PORTE RE7 RE6 LATE LATE Data Output Register TRISE PORTE Data Direction bits Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 RE5 RE4 RE3 RE2 ...
Page 134
... MOVLW 0x07 ; MOVWF CMCON ; Turn off comparators MOVLW 0x0F ; MOVWF ADCON1 ; Set PORTF as digital I/O MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF0 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs Preliminary 2004 Microchip Technology Inc. ...
Page 135
... ADCON1 — — CMCON C2OUT C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATF<0> data output; not affected by analog input PORTF<0> data input; disabled when analog input enabled. ...
Page 136
... PORTG ; Initialize PORTG by ; clearing output ; data latches CLRF LATG ; Alternate method ; to clear output ; data latches MOVLW 0x04 ; Value used to ; initialize data ; direction MOVWF TRISG ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as inputs Preliminary ) is an input PP INITIALIZING PORTG 2004 Microchip Technology Inc. ...
Page 137
... LATG — — TRISG — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: RG5 is available as an input only when MCLR is disabled. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATG<0> data output PORTG< ...
Page 138
... EXAMPLE 10-8: CLRF PORTH CLRF LATH MOVLW 0CFh MOVWF TRISH Preliminary INITIALIZING PORTH ; Initialize PORTH by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs 2004 Microchip Technology Inc. ...
Page 139
... TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name Bit 7 Bit 6 TRISH PORTH Data Direction Control Register PORTH Read PORTH pin/Write PORTH Data Latch LATH Read PORTH Data Latch/Write PORTH Data Latch 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATH<0> data output PORTH< ...
Page 140
... EXAMPLE 10-9: CLRF PORTJ CLRF LATJ MOVLW 0xCF MOVWF TRISJ Preliminary INITIALIZING PORTJ ; Initialize PORTG by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs 2004 Microchip Technology Inc. ...
Page 141
... TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name Bit 7 Bit 6 PORTJ Read PORTJ pin/Write PORTJ Data Latch LATJ LATJ Data Output Register TRISJ Data Direction Control Register for PORTJ 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATJ<0> data output PORTJ< ...
Page 142
... RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pin has protection diodes to V Preliminary PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Q RDx pin TTL Read RD TTL Chip Select CS TTL Write WR TTL and 2004 Microchip Technology Inc. ...
Page 143
... Value at POR FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared ...
Page 144
... IBOV PSPMODE — TMR0IE INT0IE RBIE TMR0IF RC1IF TX1IF SSPIF CCP1IF RC1IE TX1IE SSPIE CCP1IE RC1IP TX1IP SSPIP CCP1IP Preliminary Reset Bit 1 Bit 0 Values on Page — — — 59 INT0IF RBIF 57 TMR2IF TMR1IF 59 TMR2IE TMR1IE 59 TMR2IP TMR1IP 59 2004 Microchip Technology Inc. ...
Page 145
... Prescale value Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 146
... Sync with Internal TMR0L Clocks Delay Preliminary ). There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2004 Microchip Technology Inc. ...
Page 147
... GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT TRISA PORTA Data Direction Register Legend: Shaded cells are not used by Timer0. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
Page 148
... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 146 Preliminary 2004 Microchip Technology Inc. ...
Page 149
... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 150
... Special Event Trigger) 8 Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus 2004 Microchip Technology Inc. ...
Page 151
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 152
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary 2004 Microchip Technology Inc. ...
Page 153
... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 154
... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 152 Preliminary 2004 Microchip Technology Inc. ...
Page 155
... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 156
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSPIF CCP1IF TX1IE SSPIE CCP1IE TX1IP SSPIP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 57 TMR2IF TMR1IF 59 TMR2IE TMR1IE 59 TMR2IP TMR1IP 2004 Microchip Technology Inc. ...
Page 157
... Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
Page 158
... TCCPx Preliminary 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR3L Write TMR3L 8 8 TMR3H 8 8 Internal Data Bus 2004 Microchip Technology Inc. ...
Page 159
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 160
... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 158 Preliminary 2004 Microchip Technology Inc. ...
Page 161
... For CCP3, the special event trigger is not available. This mode functions the same as Compare Generate Interrupt mode (CCP3M3:CCP3M0 = 1010). Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Each CCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. ...
Page 162
... Timer3 is used for all Capture and Compare operations for all three CCP modules. Timer2 is used for PWM oper- ations for all three CCP modules. Timer1 is not used. All modules may share Timer2 and Timer3 resources as common time bases. 2004 Microchip Technology Inc. ...
Page 163
... CCP2CON<3:0> CCP2 pin Prescaler ÷ Q1:Q4 CCP3CON<3:0> CCP3 pin Prescaler ÷ 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 15.2.1 CCP PIN CONFIGURATION In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. Note: If RC1/CCP2 or RE7/CCP2 is configured as an output, a write to the port can cause a capture condition ...
Page 164
... A/D conversion even when the A/D converter is enabled. CCP3 is not equipped with a special event trigger. Selecting the Compare Special Event Trigger mode for this device (CCP3M3:CCP3M0 = 1011) is functionally the same as selecting the Generate Software Interrupt mode (CCP3M3:CCP3M0 = 1010). Preliminary 2004 Microchip Technology Inc. ...
Page 165
... FIGURE 15-3: COMPARE MODE OPERATION BLOCK DIAGRAM T3CCP2 0 1 T3CCP1 TMR1H TMR1L 0 TMR3H TMR3L 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Special Event Trigger (Timer1/Timer3 Reset) Set CCP1IF Output Compare Comparator Match Logic 4 CCPR1H CCPR1L CCP1CON<3:0> Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) ...
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... Preliminary Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 57 PD POR BOR 58 TMR2IF TMR1IF 59 TMR2IE TMR1IE 59 TMR2IP TMR1IP 59 TMR3IF CCP2IF 59 TMR3IE CCP2IE 59 TMR3IP CCP2IP 59 — — CCP3IF 59 — — CCP3IE 59 — — CCP3IP TMR1CS TMR1ON TMR3CS TMR3ON 2004 Microchip Technology Inc. ...
Page 167
... Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A PWM output (Figure 15-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
Page 168
... Timer2 by writing to T2CON. 5. Configure the CCP2 module for PWM operation. 9.77 kHz 39.06 kHz FFh FFh Preliminary F OSC --------------- log F PWM = -----------------------------bits log 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 2004 Microchip Technology Inc. ...
Page 169
... CCP2CON — — CCPR3L Capture/Compare/PWM Register 3 (LSB) CCPR3H Capture/Compare/PWM Register3 (MSB) CCP3CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RBIE TMR0IF — RI ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635A-page 168 Preliminary 2004 Microchip Technology Inc. ...
Page 171
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
Page 172
... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-0 R-0 R bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 173
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 /64 OSC ...
Page 174
... Example 16-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. Preliminary 2004 Microchip Technology Inc. ...
Page 175
... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.3.4 TYPICAL CONNECTION Figure 16-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
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... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 3 bit 2 bit 1 Preliminary ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ 2004 Microchip Technology Inc. ...
Page 177
... SSPIF Interrupt Flag SSPSR to SSPBUF 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39635A-page 176 bit 6 bit 3 bit 2 bit 5 bit 4 bit 6 bit 5 bit 4 bit 2 bit 3 Preliminary bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ 2004 Microchip Technology Inc. ...
Page 179
... WCOL SSPOV SSPSTAT SMP CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 16.3.10 ...
Page 180
... SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg) Preliminary 2 C operation mode operation. The 2 C Slave mode. When 2004 Microchip Technology Inc. ...
Page 181
... Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2 C MODE) R-0 R-0 ...
Page 182
... SSPM2 2 (1) (2) /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 (2) (2) (2) SSPM1 SSPM0 bit 0 C conditions were not valid for x = Bit is unknown 2004 Microchip Technology Inc. ...
Page 183
... Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive the I the SSPBUF may not be written (or writes to the SSPBUF are disabled). Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2 C MODE) R/W-0 R/W-0 R/W-0 ...
Page 184
... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Preliminary 2004 Microchip Technology Inc. ...
Page 185
... The clock must be released by setting bit CKP (SSPCON<4>). See Section 16.4.4 “Clock Stretching” for more detail. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
Page 186
... PIC18F6310/6410/8310/8410 2 FIGURE 16-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39635A-page 184 Preliminary 2004 Microchip Technology Inc. ...
Page 187
... FIGURE 16-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Preliminary DS39635A-page 185 ...
Page 188
... PIC18F6310/6410/8310/8410 2 FIGURE 16-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39635A-page 186 Preliminary 2004 Microchip Technology Inc. ...
Page 189
... FIGURE 16-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Preliminary DS39635A-page 187 ...
Page 190
... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 16-11). Preliminary 2004 Microchip Technology Inc. ...
Page 191
... SDA DX SCL CKP WR SSPCON 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 16-12) ...
Page 192
... PIC18F6310/6410/8310/8410 2 FIGURE 16-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39635A-page 190 Preliminary 2004 Microchip Technology Inc. ...
Page 193
... FIGURE 16-14: I C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Preliminary DS39635A-page 191 ...
Page 194
... UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 16-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Preliminary Receiving Data ACK ‘0’ ‘1’ 2004 Microchip Technology Inc. ...
Page 195
... Generate a Stop condition on SDA and SCL. FIGURE 16-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
Page 196
... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. Preliminary 2004 Microchip Technology Inc. ...
Page 197
... The I C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...
Page 198
... DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count Preliminary 03h 02h 2004 Microchip Technology Inc. ...
Page 199
... FIGURE 16-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL 2004 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Note: If, at the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the ...
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... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start Preliminary 1st bit T BRG 2004 Microchip Technology Inc. ...