PIC18F6410-I/PT Microchip Technology, PIC18F6410-I/PT Datasheet - Page 59

• Manufacturer Part Number: PIC18F6410-I/PT
• Description: IC PIC MCU FLASH 8KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6410-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.5
PIC18F6310/6410/8310/8410
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
5.5.1
The
PIC18F6310/6410/8310/8410 devices is an 11-bit
counter which uses the INTRC source as the clock
input. This yields an approximate time interval of
2048 x 32 s = 65.6 ms. While the PWRT is counting,
the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC Parameter 33 for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
5.5.2
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (Parameter 33). This ensures that
the crystal oscillator or resonator has started and is
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes, and only on Power-on Reset or on exit
from most power-managed modes.
TABLE 5-2:
 2010 Microchip Technology Inc.
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
Note 1:
Configuration
2:
Oscillator
Power-up
Device Reset Timers
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2 ms is the nominal time required for the PLL to lock.
POWER-UP TIMER (PWRT)
OSCILLATOR START-UP
TIMER (OST)
TIME-OUT IN VARIOUS SITUATIONS
Timer
66 ms
66 ms
(1)
(PWRT)
devices
PWRTEN = 0
+ 1024 T
(1)
66 ms
66 ms
66 ms
+ 1024 T
incorporate
Power-up
OSC
(1)
(1)
(1)
of
PIC18F6310/6410/8310/8410
+ 2 ms
OSC
the
(2)
(2)
and Brown-out
5.5.3
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A separate timer
is used to provide a fixed time-out that is sufficient for
the PLL to lock to the main oscillator frequency. This
PLL lock time-out (T
the oscillator start-up time-out.
5.5.4
On power-up, the time-out sequence is as follows:
1.
2.
The total time-out will vary based on oscillator
configuration and the status of the PWRT.
Figure
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure
synchronize more than one PIC18FXXXX device
operating in parallel.
1024 T
PWRTEN = 1
After the POR pulse has cleared, PWRT
time-out is invoked (if enabled).
Then, the OST is activated.
1024 T
5-4,
OSC
5-5). This is useful for testing purposes or to
—
—
—
PLL LOCK TIME-OUT
TIME-OUT SEQUENCE
+ 2 ms
Figure
OSC
(2)
5-5,
PLL
) is typically 2 ms and follows
Figure 5-6
5-3
Power-Managed Mode
1024 T
through
1024 T
and
Exit from
DS39635C-page 59
OSC
—
—
—
Figure 5-7
5-6
+ 2 ms
OSC
Figure
also apply
(2)
5-3,
all