IDT72V36100 IDT [Integrated Device Technology], IDT72V36100 Datasheet - Page 5

• Manufacturer Part Number: IDT72V36100
• Manufacturer: IDT [Integrated Device Technology]

NOTE:
1. Inputs should not change state after Master Reset.
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
Symbol
D
MRS
PRS
RT
FWFT/SI First Word Fall
OW
IW
BM
BE
RM
PFM
IP
FSEL0
FSEL1
WCLK
WEN
RCLK
REN
OE
SEN
LD
FF/IR
EF/OR
PAF
PAE
HF
Q
0
0
(1)
–D
(1)
–Q
(1)
(1)
(1)
(1)
(1)
35
35
(1)
(1)
Data Inputs
Master Reset
Partial Reset
Retransmit
Through/Serial In
Output Width
Input Width
Bus-Matching
Big-Endian/
Little-Endian
Retransmit Timing
Mode
Programmable
Flag Mode
Interspersed Parity I
Flag Select Bit 0
Flag Select Bit 1
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Serial Enable
Load
Full Flag/
Empty Flag/
Output Ready
Programmable
Almost-Full Flag
Programmable
Almost-Empty Flag
Half-Full Flag
Data Outputs
Name
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
will select Synchronous Programmable flag timing mode.
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the
FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable
flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero
latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the
existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings. RT is useful to reread data from the first physical location of the FIFO.
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
This pin, along with OW and MB, selects the bus width of the write port. See Table 1 for bus size configuration.
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size configuration.
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
normal latency mode.
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity
mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect
the data written to and read from the FIFO.
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the programmable
flags PAE and PAF. There are up to eight possible settings available.
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the programmable
flags PAE and PAF. There are up to eight possible settings available.
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable registers
for parallel programming, and when enabled by SEN, the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the programmable
registers.
REN enables RCLK for reading data from the FIFO memory and offset registers.
SEN enables serial loading of programmable flag offsets.
This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1, determines
one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offset registers.
In the IDT Standard mode, the FF function is selected. FF indicates whether or Input Ready not the FIFO memory
is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing
to the FIFO memory.
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
state. Outputs are not 5V tolerant regardless of the state of OE.
Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
functions as a serial input for loading offset registers.
will select Little-Endian format.
OE controls the output impedance of Q
TM
36-BIT FIFO
5
n.
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES