IDT72V36100 IDT [Integrated Device Technology], IDT72V36100 Datasheet - Page 35

• Manufacturer Part Number: IDT72V36100
• Manufacturer: IDT [Integrated Device Technology]

the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
where N is the number of FIFOs in the expansion and T
Note that extra cycles should be added for the possibility that the t
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
Figure 24. Block Diagram of 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 and 262,144 x 36 Depth Expansion
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
FWFT/SI
INPUT READY
DATA IN
WRITE CLOCK
WRITE ENABLE
For an empty expansion configuration, the amount of time it takes for OR of
The "ripple down" delay is only noticeable for the first word written to an empty
The first free location created by reading from a full depth expansion
n
(N – 1)*(4*transfer clock) + 3*T
Dn
WEN
IR
WCLK
72V36100
72V36110
FWFT/SI
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
IDT
TRANSFER CLOCK
RCLK
RCLK
REN
RCLK
OE
OR
Qn
is the RCLK period.
SKEW1
TM
GND
36-BIT FIFO
n
35
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
For a full expansion configuration, the amount of time it takes for IR of the first
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
WCLK
IR
WEN
Dn
(N – 1)*(3*transfer clock) + 2 T
72V36100
72V36110
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
FWFT/SI
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
OR
Qn
OE
TEMPERATURE RANGES
WCLK
OUTPUT ENABLE
n
OUTPUT READY
READ ENABLE
WCLK
READ CLOCK
DATA OUT
4667 drw 29
is the WCLK
SKEW1