IDT72V36100 IDT [Integrated Device Technology], IDT72V36100 Datasheet - Page 17

• Manufacturer Part Number: IDT72V36100
• Manufacturer: IDT [Integrated Device Technology]

DATA IN (D
(D
MASTER RESET ( MRS )
state. This operation sets the internal read and write pointers to the first location
of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
during the Master Reset cycle.
Reset is required after power up, before a write operation can take place. MRS
is asynchronous.
PARTIAL RESET ( PRS )
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH,
and HF goes HIGH.
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall
Through mode is active, then OR will go HIGH, and IR will go LOW.
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes. PRS is asynchronous.
operation, when reprogramming programmable flag offset settings may not be
convenient.
RETRANSMIT ( RT )
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of the memory.
REN and WEN must be HIGH before bringing RT LOW. When zero latency is
utilized, REN does not need to be HIGH before bringing RT LOW.
Retransmit setup by setting EF LOW. The change in level will only be noticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
may begin starting with the first location in memory. Since IDT Standard mode
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
0
Data inputs for 36-bit wide data (D
A Master Reset is accomplished whenever the MRS input is taken to a LOW
All control settings such as OW, IW, BM, BE, RM, PFM and IP are defined
During a Master Reset, the output register is initialized to all zeroes. A Master
See Figure 5, Master Reset Timing, for the relevant timing diagram.
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
Whichever mode is active at the time of Partial Reset, IDT Standard mode
Following Partial Reset, all values held in the offset registers remain
A Partial Reset is useful for resetting the device during the course of
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
The Retransmit operation allows data that has already been read to be
Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
When EF goes HIGH, Retransmit setup is complete and read operations
- D
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
17
) or data inputs for 9-bit wide data (D
0
- D
n
)
0
- D
35
), data inputs for 18-bit wide data
0
- D
8
).
TM
36-BIT FIFO
17
is selected, every word read including the first word following Retransmit setup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
Retransmit Mode (RM) pin during a Master Reset. This can be applied to both
IDT Standard mode and FWFT mode.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
SI input determines whether the device will operate in IDT Standard mode or
First Word Fall Through (FWFT) mode.
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Q
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Q
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
Serial programming using the FWFT/SI pin functions the same way in both IDT
Standard and FWFT modes.
WRITE CLOCK (WCLK)
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating HF flag to LOW.) The Write and Read Clocks can either be
independent or coincident.
WRITE ENABLE ( WEN )
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
cycle.
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + t
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
When OR goes LOW, Retransmit setup is complete; at the same time, the
In Retransmit operation, zero latency mode can be selected using the
This is a dual purpose pin. During Master Reset, the state of the FWFT/
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF
A write cycle is initiated on the rising edge of the WCLK input. Data setup
When the WEN input is LOW, data may be loaded into the FIFO RAM array
When WEN is HIGH, no new data is written in the RAM array on each WCLK
To prevent data overflow in the IDT Standard mode, FF will go LOW,
SKEW
after the RCLK cycle.
n)
. It also uses Input Ready (IR) to indicate
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
n
after three RCLK