EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 69

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 62. I2C0SSTA MMR Bit Descriptions
Bit
31:15
14
13
12:11
10
9:8
7
6
5
4
3
2
1
0
Value
00
01
10
11
00
01
10
11
Description
Reserved. These bits should be written as 0.
Start Decode Bit. Set by hardware if the device
receives a valid start + matching address.
Cleared by an I
general call reset.
Repeated Start Decode Bit. Set by hardware
if the device receives a valid repeated start and
matching address. Cleared by an I
condition, a read of the I2CSSTA register,
or an I
ID Decode Bits.
Received Address Matched ID Register 0.
Received Address Matched ID Register 1.
Received Address Matched ID Register 2.
Received Address Matched ID Register 3.
Stop After Start and Matching Address
Interrupt. Set by hardware if the slave device
receives an I
I
Cleared by a read of the I2C0SSTA register.
General Call ID.
No General Call.
General Call Reset and Program Address.
General Call Program Address.
General Call Matching Alternative ID.
General Call Interrupt. Set if the slave device
receives a general call of any type. Cleared by
setting Bit 8 of the I2CxCFG register. If it is a
general call reset, all registers are at their
default values. If it is a hardware general call,
the Rx FIFO holds the second byte of the
general call. This is similar to the I2C0ALT
register (unless it is a general call to reprogram
the device address). For more details, see the I
bus specification, Version 2.1, Jan. 2000.
Slave Busy. Set automatically if the slave is busy.
Cleared automatically.
No ACK. Set if master asking for data and no
data is available. Cleared automatically by
reading the I2C0SSTA register.
Slave Receive FIFO Overflow. Set automatically
if the slave receive FIFO is overflowing. Cleared
automatically by reading the I2C0SSTA register.
Slave Receive IRQ. Set after receiving data.
Cleared automatically by reading the I2C0SRX
register or flushing the FIFO.
Slave Transmit IRQ. Set at the end of a trans-
mission. Cleared automatically by writing to the
I2C0STX register.
Slave Transmit FIFO Underflow. Set automatically if
the slave transmit FIFO is underflowing. Cleared
automatically by writing to the I2C0SSTA register.
Slave Transmit FIFO Not Full. Set automatically if
the slave transmit FIFO is not full. Cleared auto-
matically by writing twice to the I2C0STX register.
2
C start condition and matching address.
2
C general call reset.
2
C stop condition after a previous
2
C stop condition or an I
2
C stop
2
C
Rev. B | Page 69 of 92
2
C
I2CxSRX Registers
Name
I2C0SRX
I2C1SRX
I2CxSRX are receive registers for the slave channel.
I2CxSTX Registers
Name
I2C0STX
I2C1STX
I2CxSTX are transmit registers for the slave channel.
I2CxMRX Registers
Name
I2C0MRX
I2C1MRX
I2CxMRX are receive registers for the master channel.
I2CxMTX Registers
Name
I2C0MTX
I2C1MTX
I2CxMTX are transmit registers for the master channel.
I2CxCNT Registers
Name
I2C0CNT
I2C1CNT
I2CxCNT are 3-bit, master receive, data count registers. If a master
read transfer sequence is initiated, the I2CxCNT registers denote
the number of bytes (−1) to be read from the slave device. By
default, this counter is 0, which corresponds to the 1 byte expected.
I2CxADR Registers
Name
I2C0ADR
I2C1ADR
I2CxADR are master address byte registers. The I2CxADR
value is the device address that the master wants to
communicate with. It automatically transmits at the start of a
master transfer sequence if there is no valid data in the
I2CxMTX register when the master enable bit is set.
I2CxBYTE Registers
Name
I2C0BYTE
I2C1BYTE
I2CxBYTE are broadcast byte registers. Data written to these
register do not go through the TxFIFO. This data is transmitted
at the start of a transfer sequence before the address. Once the
byte has been transmitted and acknowledged, the I
another byte written in I2CxBYTE or an address written to the
address register.
ADuC7019/20/21/22/24/25/26/27/28
Address
0xFFFF0808
0xFFFF0908
Address
0xFFFF080C
0xFFFF090C
Address
0xFFFF0810
0xFFFF0910
Address
0xFFFF0814
0xFFFF0914
Address
0xFFFF0818
0xFFFF0918
Address
0xFFFF081C
0xFFFF091C
Address
0xFFFF0824
0xFFFF0924
Default Value
0x00
0x00
Default Value
0x00
0x00
Default Value
0x00
0x00
Default Value
0x00
0x00
Default Value
0x00
0x00
Default Value
0x00
0x00
Default Value
0x00
0x00
2
C expects
Access
R
R
Access
W
W
Access
R
R
Access
W
W
Access
R/W
R/W
Access
R/W
R/W
Access
R/W
R/W