EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 48
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EVAL-ADUC7026QSP
Manufacturer Part Number
EVAL-ADUC7026QSP
Description
KIT DEV FOR ADUC7026/7027
Manufacturer
Analog Devices Inc
Datasheet
1.EVAL-ADUC7026QSP.pdf
(92 pages)
Specifications of EVAL-ADUC7026QSP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EVAL-ADUC7026QSPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
- Current page: 48 of 92
- Download datasheet (2Mb)
ADuC7019/20/21/22/24/25/26/27/28
Reset Operation
There are four kinds of reset: external, power-on, watchdog
expiation, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset is external.
REMAP Register
Name
REMAP
1
Table 25. REMAP MMR Bit Designations
Bit
4
3
2:1
0
Depends on model.
Name
Remap
Address
0xFFFF0220
Description
Read-Only Bit. Indicates the size of the
Flash/EE memory available. If this bit is set,
only 32 kB of Flash/EE memory is available.
Read-Only Bit. Indicates the size of the SRAM
memory available. If this bit is set, only 4 kB of
SRAM is available.
Reserved.
Remap Bit. Set by user to remap the SRAM to
Address 0x00000000. Cleared automatically
after reset to remap the Flash/EE memory to
Address 0x00000000.
Default Value
0xXX
1
Access
R/W
Rev. B | Page 48 of 92
RSTSTA Register
Name
RSTSTA
Table 26. RSTSTA MMR Bit Designations
Bit
7:3
2
1
0
RSTCLR Register
Name
RSTCLR
Note that to clear the RSTSTA register, users must write the
Value 0x07 to the RSTCLR register.
Description
Reserved.
Software Reset. Set by user to force a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Watchdog Timeout. Set automatically when a
watchdog timeout occurs. Cleared by setting the
corresponding bit in RSTCLR.
Power-On Reset. Set automatically when a power-on
reset occurs. Cleared by setting the corresponding bit in
RSTCLR.
Address
0xFFFF0230
Address
0xFFFF0234
Default Value
0x01
Default Value
0x00
Access
R/W
Access
R/W
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