EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 61

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 40. GPIO Pin Function Descriptions
Port
0
1
2
3
4
1
2
GPxCON Registers
Name
GP0CON
GP1CON
GP2CON
GP3CON
GP4CON
When configured in Mode 1, P0.7 is ECLK by default, or core clock output.
To configure it as a clock input, the MDCLK bits in PLLCON must be set to 11.
The CONV
Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
START
signal is active in all modes of P2.0.
00
GPIO
GPIO
GPIO
GPIO
GPIO/IRQ0
GPIO/IRQ1
GPIO/T1
GPIO
GPIO/T1
GPIO
GPIO
GPIO
GPIO/IRQ2
GPIO/IRQ3
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Address
0xFFFFF400
0xFFFFF404
0xFFFFF408
0xFFFFF40C
0xFFFFF410
01
PWM2
PWM2
TRST
PWM
ADC
ECLK/XCLK
SOUT
RTS
CTS
DSR
DTR
CONV
PWM0
PWM0
PWM0
PWM0
PWM1
PWM1
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
PWM
PWM
Configuration
CMP
MRST
SIN
RI
DCD
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
BUSY
TRIP
TRIP
SYNC
START
H
L
H
L
H
L
H
L
H
L
H
L
H
L
2
1
10
MS0
BLE
BHE
A16
MS1
MS2
SIN
SCL0
SDA0
SCL1
SDA1
CLK
MISO
MOSI
CSL
SOUT
WS
RS
AE
MS0
MS1
MS2
MS3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
Access
R/W
R/W
R/W
R/W
R/W
11
PLAI[7]
ADC
PLAO[1]
PLAO[2]
PLAO[3]
PLAO[4]
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[5]
PLAO[6]
PLAO[7]
PLAI[8]
PLAI[9]
PLAI[10]
PLAI[11]
PLAI[12]
PLAI[13]
PLAI[14]
PLAI[15]
PLAO[8]
PLAO[9]
PLAO[10]
PLAO[11]
PLAO[12]
PLAO[13]
PLAO[14]
PLAO[15]
BUSY
Rev. B | Page 61 of 92
GPxCON are the Port x control registers, which select the
function of each pin of Port x as described in Table 41.
Table 41. GPxCON MMR Bit Descriptions
Bit
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
GPxPAR Registers
Name
GP0PAR
GP1PAR
GPxPAR program the parameters for Port 0 and Port 1. Note that
the GPxDAT MMR must always be written after changing the
GPxPAR MMR.
Table 42. GPxPAR MMR Bit Descriptions
Bit
31:29
28
27:25
24
23:21
20
19:17
16
15:13
12
11:9
8
7:5
4
3:1
0
ADuC7019/20/21/22/24/25/26/27/28
Description
Reserved.
Select Function of Px.7 Pin.
Reserved.
Select Function of Px.6 Pin.
Reserved.
Select Function of Px.5 Pin.
Reserved.
Select Function of Px.4 Pin.
Reserved.
Select Function of Px.3 Pin.
Reserved.
Select Function of Px.2 Pin.
Reserved.
Select Function of Px.1 Pin.
Reserved.
Select Function of Px.0 Pin.
Address
0xFFFFF42C
0xFFFFF43C
Description
Reserved.
Pull-Up Disable Px.7.
Reserved.
Pull-Up Disable Px.6.
Reserved.
Pull-Up Disable Px.5.
Reserved.
Pull-Up Disable Px.4.
Reserved.
Pull-Up Disable Px.3.
Reserved.
Pull-Up Disable Px.2.
Reserved.
Pull-Up Disable Px.1.
Reserved.
Pull-Up Disable Px.0.
Default Value
0x20000000
0x00000000
Access
R/W
R/W