EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 55

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DESCRIPTION OF THE PWM BLOCK
A functional block diagram of the PWM controller is shown in
Figure 57. The generation of the six output PWM signals on
Pin PWM0
important blocks.
•
•
•
•
The PWM controller is driven by the ADuC7019/20/21/22/24/
25/26/27/28 core clock frequency and is capable of generating
two interrupts to the ARM core. One interrupt is generated on
the occurrence of a PWMSYNC pulse, and the other is
generated on the occurrence of any PWM shutdown action.
3-Phase Timing Unit
PWM Switching Frequency (PWMDAT0 MMR)
The PWM switching frequency is controlled by the PWM
period register, PWMDAT0. The fundamental timing unit of
the PWM controller is
where f
The 3-phase PWM timing unit. The core of the PWM
controller, this block generates three pairs of complemented
and dead-time-adjusted, center-based PWM signals. This
unit also generates the internal synchronization pulse,
PWMSYNC. It also controls whether the external PWM
pin is used or not.
The output control unit. This block can redirect the
outputs of the 3-phase timing unit for each channel to
either the high-side or low-side output. In addition, the
output control unit allows individual enabling/disabling of
each of the six PWM output signals.
The gate drive unit. This block can generate the high
frequency chopping and its subsequent mixing with the
PWM signals.
The PWM shutdown controller. This block takes care of
the PWM shutdown via the PWM
correct reset signal for the timing unit.
t
CORE
CORE
= 1/f
H
is the core frequency of the MicroConverter.
to Pin PWM2
CORE
L
TO INTERRUPT
CONTROLLER
is controlled by the following four
CORE CLOCK
TRIP
CONTROLLER
SHUTDOWN
pin and generates the
PWM
CONFIGURATION
Figure 57. Overview of the PWM Controller
REGISTERS DUTY CYCLE
PWMDAT0
PWMDAT1
PWMDAT2
PWMCON
THREE-PHASE
PWM TIMING
SYNC
Rev. B | Page 55 of 92
UNIT
REGISTERS
PWMCH0
PWMCH1
PWMCH2
SYNC
Therefore, for a 41.78 MHz f
is 24 ns. The value written to the PWMDAT0 register is effectively
the number of f
required PWMDAT0 value is a function of the desired PWM
switching frequency (f
Therefore, the PWM switching period, t
The largest value that can be written to the 16-bit PWMDAT0
MMR is 0xFFFF = 65535, which corresponds to a minimum
PWM switching frequency of
Note that a PWMDAT0 value of 0 and 1 are not defined and
should not be used.
PWM Switching Dead Time (PWMDAT1 MMR)
The second important parameter that must be set up in the initial
configuration of the PWM block is the switching dead time. This
is a short delay time introduced between turning off one PWM
signal (0H, for example) and turning on the complementary
signal (0L). This short time delay is introduced to permit the
power switch to be turned off (in this case, 0H) to completely
recover its blocking capability before the complementary switch is
turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link
capacitor of a typical voltage source inverter.
The dead time is controlled by the 10-bit, read/write PWMDAT1
register. There is only one dead-time register that controls the dead
time inserted into all three pairs of PWM output signals. The dead
time, t
Therefore, a PWMDAT1 value of 0x00A (= 10), introduces
a 426 ns delay between the turn-off on any PWM signal (0H,
for example) and the turn-on of its complementary signal (0L).
The amount of the dead time can therefore be programmed in
increments of 2t
CONTROL
OUTPUT
PWMEN
UNIT
PWMDAT0 = f
t
f
t
PWM(min)
S
D
ADuC7019/20/21/22/24/25/26/27/28
D
= 2 × PWMDAT0 × t
= PWMDAT1 × 2 × t
, is related to the value in the PWMDAT1 register by:
PWMCFG
= 41.78 × 10
DRIVE
GATE
UNIT
CORE
CORE
clock increments in ½ a PWM period. The
CORE
(or 49 ns for a 41.78 MHz core clock).
PWN
/(2 × f
6
) and is given by
/(2 × 65535) = 318.75 Hz
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
PWM
PWM
CORE
CORE
CORE
PWM
SYNC
TRIP
, the fundamental time increment
H
L
H
L
H
L
)
S
, can be written as