EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 52

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADuC7019/20/21/22/24/25/26/27/28
Example source code:
3)) //ensures timer value loaded
//enable T2 interrupt
// Set Core into Nap mode
In noisy environments, noise can couple to the external crystal
pins, and PLL may lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is only serviced when the lock is restored.
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA can determine if the reset
came from the watchdog timer.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in
Mode 1. The external clock can be up to 44 MHz, providing
the tolerance is 1%.
Table 31. Operating Modes
Mode
Active
Pause
Nap
Sleep
Stop
Table 32. Typical Current Consumption at 25°C in mA.
PC[2:0]
000
001
010
011
100
while ((T2VAL == t2val_old) || (T2VAL >
IRQEN = 0x10;
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27;
POWKEY2 = 0xF4;
T2LD = 5;
TCON = 0x480;
Core
X
Mode
Active
Pause
Nap
Sleep
Stop
Peripherals
X
X
CD = 0
33.1
22.7
3.8
0.4
0.4
PLL
X
X
X
CD = 1
21.2
13.3
3.8
0.4
0.4
XTAL/T2/T3
X
X
X
X
Rev. B | Page 52 of 92
CD = 2
13.8
8.5
3.8
0.4
0.4
Example source code:
3)) //ensures timer value loaded
//enable T2 interrupt
Set Core into Nap mode
Power Control System
A choice of operating modes is available on the ADuC7019/20/
21/22/24/25/26/27/28. Table 31 describes what part is powered
on in the different modes and indicates the power-up time.
Table 32 gives some typical values of the total current consump-
tion (analog + digital supply currents) in the different modes,
depending on the clock divider bits. The ADC is turned off. Note
that these values also include current consumption of the
regulator and other parts on the test board where these values
are measured.
IRQ0 to IRQ3
X
X
X
X
X
CD = 3
10
6.1
3.8
0.4
0.4
while ((T2VAL == t2val_old) || (T2VAL >
IRQEN = 0x10;
PLLKEY1 = 0xAA;
PLLCON = 0x03; //Select external clock
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27;
POWKEY2 = 0xF4;
T2LD = 5;
TCON = 0x480;
CD = 4
8.1
4.9
3.8
0.4
0.4
130 ms at CD = 0
24 ns at CD = 0; 3 μs at CD = 7
24 ns at CD = 0; 3 μs at CD = 7
Start-Up/Power-On Time
1.58 ms
1.7 ms
CD = 5
7.2
4.3
3.8
0.4
0.4
CD = 6
6.7
4
3.8
0.4
0.4
CD = 7
6.45
3.85
3.8
0.4
0.4
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