EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 51

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON,
which is described in Table 30.
CMPCON Register
Name
CMPCON
Table 30. CMPCON MMR Bit Descriptions
Bit
15:11
10
9:8
7:6
5
4:3
2
1
0
Value
00
01
10
11
00
01
10
11
00
11
01/10
Address
0xFFFF0444
Name
CMPEN
CMPIN
CMPOC
CMPOL
CMPRES
CMPHYST
CMPORI
CMPOFI
Description
Reserved.
Comparator Enable Bit. Set by user
to enable the comparator. Cleared
by user to disable the comparator.
Comparator Negative Input
Select Bits.
AV
ADC3 input.
DAC0 output.
Reserved.
Comparator Output Configuration
Bits.
Reserved.
Reserved.
Output on CMP
IRQ.
Comparator Output Logic State Bit.
When low, the comparator output
is high if the positive input (CMP0)
is above the negative input (CMP1).
When high, the comparator output
is high if the positive input is
below the negative input.
Response Time.
5 μs response time typical for large
signals (2.5 V differential).
17 μs response time typical for
small signals (0.65 mV differential).
3 μs typical.
Reserved.
Comparator Hysteresis Bit. Set by
user to have a hysteresis of about
7.5 mV. Cleared by user to have no
hysteresis.
Comparator Output Rising Edge
Interrupt. Set automatically when a
rising edge occurs on the moni-
tored voltage (CMP0). Cleared by
user by writing a 1 to this bit.
Comparator Output Falling Edge
Interrupt. Set automatically when a
falling edge occurs on the monitored
voltage (CMP0). Cleared by user.
DD
Default Value
0x0000
/2.
OUT
.
Access
R/W
Rev. B | Page 51 of 92
OSCILLATOR AND PLL—POWER CONTROL
Clocking System
Each ADuC7019/20/21/22/24/25/26/27/28 integrates a 32.768 kHz
±3% oscillator, a clock divider, and a PLL. The PLL locks onto a
multiple (1275) of the internal oscillator or an external 32.768 kHz
crystal to provide a stable 41.78 MHz clock (UCLK) for the system.
To allow power saving, the core can operate at this frequency, or
at binary submultiples of it. The actual core operating frequency,
UCLK/2
PLL clock divided by 8 (CD = 3) or 5.22 MHz. The core clock
frequency can also come from an external clock on the ECLK
pin as described in Figure 56. The core clock can be outputted
on ECLK when using an internal oscillator or external crystal.
Note that when the ECLK pin is used to output the core clock,
the output signal is not buffered and is not suitable for use as a
clock source to an external device without an external buffer.
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
External Crystal Selection
To switch to an external crystal, users must follow this procedure:
1.
2.
3.
4.
WATCHDOG
*32.768kHz ±3%
WAKEUP
TIMER
TIMER
Enable the Timer2 interrupt and configure it for a timeout
period of >120 μs.
Follow the write sequence to the PLLCON register setting
the MDCLK bits to 01 and clearing the OSEL bit.
Force the part into NAP mode by following the correct
write sequence to the POWCON register
When the part is interrupted from NAP mode by the
Timer2 interrupt source, the clock source has switched to
the external clock.
ADuC7019/20/21/22/24/25/26/27/28
CD
CORE
, is refered to as HCLK. The default core clock is the
OSCILLATOR
INT. 32kHz*
Figure 56. Clocking System
PLL
I
2
C
32.768kHz
CD
41.78MHz
UCLK
AT POWER UP
OSCILLATOR
P0.7/ECLK
CRYSTAL
/2
OCLK
CD
HCLK
PERIPHERALS
MDCLK
ANALOG
XCLKO
XCLKI
P0.7/XCLK