EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 67

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 59. SPISTA MMR Bit Descriptions
Bit
7:6
5
4
3
2
1
0
Table 60. SPICON MMR Bit Descriptions
Bit
15:13
12
11
10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
SPIRX Data Register Overflow Status Bit. Set if SPIRX is
overflowing. Cleared by reading SPIRX register.
SPIRX Data Register IRQ. Set automatically if Bit 3 or Bit 5
is set. Cleared by reading SPIRX register.
SPIRX Data Register Full Status Bit. Set automatically if a
valid data is present in the SPIRX register. Cleared by
reading SPIRX register.
SPITX Data Register Underflow Status Bit. Set auto-
matically if SPITX is underflowing. Cleared by writing in
the SPITX register.
SPITX Data Register IRQ. Set automatically if Bit 0 is clear
or Bit 2 is set. Cleared by writing in the SPITX register or if
finished transmission disabling the SPI.
SPITX Data Register Empty Status Bit. Set by writing to
SPITX to send data. This bit is set during transmission of
data. Cleared when SPITX is empty.
Description
Reserved.
Continuous Transfer
Enable.
Loop Back Enable.
Slave Output Enable.
Slave Select Input Enable.
SPIRX Overflow
Overwrite Enable.
SPITX Underflow Mode.
Transfer and Interrupt
Mode.
LSB First Transfer
Enable Bit.
Reserved.
Serial Clock Polarity
Mode Bit.
Serial Clock Phase
Mode Bit.
Master Mode Enable Bit.
SPI Enable Bit.
Function
–
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is
available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial
transfer until TX is empty. Cleared by user to disable continuous transfer. Each transfer consists of a
single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a
stall period.
Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
Set by user to enable the slave output enable. Cleared by user to disable slave output enable.
Set by user in master mode to enable the output. Cleared by user to disable master output.
Set by user, the valid data in the RX register is overwritten by the new serial byte received. Cleared by
user, the new serial byte received is discarded.
Set by user to transmit 0. Cleared by user to transmit the previous data.
Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when TX is empty.
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when RX is full.
Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first.
–
Set by user, the serial clock idles high. Cleared by user, the serial clock idles low.
Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial
clock pulses at the end of each serial bit transfer.
Set by user to enable master mode. Cleared by user to enable slave mode.
Set by user to enable the SPI. Cleared by user to disable the SPI.
Rev. B | Page 67 of 92
SPIRX Register
Name
SPIRX
SPIRX is an 8-bit read-only receive register.
SPITX Register
Name
SPITX
SPITX is an 8-bit write-only transmit register.
SPIDIV Register
Name
SPIDIV
SPIDIV is an 8-bit serial clock divider register.
SPICON Register
Name
SPICON
SPICON is a 16-bit control register.
ADuC7019/20/21/22/24/25/26/27/28
Address
0xFFFF0A04
Address
0xFFFF0A08
Address
0xFFFF0A0C
Address
0xFFFF0A10
Default Value
0x00
Default Value
0x00
Default Value
0x1B
Default Value
0x0000
Access
R
Access
W
Access
R/W
Access
R/W