EVAL-ADUC814QS Analog Devices Inc, EVAL-ADUC814QS Datasheet - Page 67

KIT DEV FOR ADUC814 QUICK START

EVAL-ADUC814QS

Manufacturer Part Number
EVAL-ADUC814QS
Description
KIT DEV FOR ADUC814 QUICK START
Manufacturer
Analog Devices Inc
Series
QuickStart™ Kitr
Type
8052-corer
Datasheet

Specifications of EVAL-ADUC814QS

Contents
Evaluation Board, Power Supply, Cable, Software and Documentation
For Use With/related Products
ADuC814
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 37. SPI Master Mode Timing (CPHA = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0, respectively.
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
Characterized under the following conditions:
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Data Output Valid after SCLOCK Edge
Data Output Setup before SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
MOSI
MISO
t
DOSU
t
DSU
MSB IN
1
1
t
MSB
DHD
t
SH
t
Figure 64. SPI Master Mode Timing (CPHA = 0)
DF
t
DAV
t
SL
Rev. A | Page 67 of 72
t
DR
BITS 6–1
BITS 6–1
LSB IN
t
SR
LSB
Min
100
100
t
SF
Typ
630
630
10
10
10
10
Max
50
150
25
25
25
25
ADuC814
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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