EVAL-ADUC814QS Analog Devices Inc, EVAL-ADUC814QS Datasheet - Page 41

• Manufacturer Part Number: EVAL-ADUC814QS
• Description: KIT DEV FOR ADUC814 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: 8052-corer

Specifications of EVAL-ADUC814QS

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• For Use With/related Products: ADuC814
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
or interrupt within a reasonable amount of time if the ADuC814
enters an erroneous state, possibly due to a programming error,
electrical noise, or RFI. The watchdog function can be disabled
by clearing the WDE (watchdog enable) bit in the watchdog
control (WDCON) SFR. When enabled, the watchdog circuit
generates a system reset or interrupt (WDS) if the user program
fails to set the watchdog (WDE) bit within a predetermined
amount of time (see PRE3–0 bits in WDCON). The watchdog
timer itself is a 16-bit counter that is clocked at 32.768 kHz. The
watchdog timeout interval can be adjusted via the PRE3–0 bits
Table 15. WDCON SFR Bit Designation
Bit No.
7
6
5
4
3
2
1
0
PRE3
Name
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
PRE2
Description
Watchdog Timer Prescale Bits.
The watchdog timeout period is given by the equation
where f
PRE3
0
0
0
0
0
0
0
0
1
PRE3–0 > 1001
Watchdog Interrupt Request.
If this bit is set by the user, the watchdog generates an interrupt response instead of a system reset when the
watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction and it is also a fixed,
high-priority interrupt.
If the watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler is used
to set the timeout period in which an interrupt is generated. (See Table 33, Note 1, in the Interrupt System section.)
Watchdog Status Bit.
Set by the watchdog controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within the watchdog
timeout period, the watchdog generates a reset or interrupt, depending on WDIR.
Cleared under the following conditions: User writes 0, Watchdog Reset (WDIR = 0); Hardware Reset; PSM Interrupt.
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and followed
immediately by a write instruction to the WDCON SFR. For example:
CLR EA
SETB WDWR
MOV WDCON, #72H
SET B EA
PLL
t
= 32.768 kHz and PRE is defined as follows:
WD
= (2
PRE2
0
0
0
0
1
1
1
1
0
PRE
PRE1
× (2
; disable interrupts while writing to WDT
; allow write to WDCON
; enable WDT for 2.0s timeout
; enable interrupts again (if rqd)
9
/f
PLL
))
PRE1
0
0
1
1
0
0
1
1
0
PRE0
Rev. A | Page 41 of 72
PRE0
0
1
0
1
0
1
0
1
0
in WDCON. Full control and status of the watchdog timer
function can be controlled via the watchdog timer control SFR
(WDCON). The WDCON SFR can be written only by the user
software if the double write sequence (WDWR) described in
Table 15 is initiated on every write access to the WDCON SFR.
WDCON
SFR Address
Power-On Default
Bit Addressable
WDIR
Timeout Period (ms)
15.6
31.2
62.5
125
250
500
1000
2000
0.0
WDS
Watchdog Timer Control Register
C0H
10H
Yes
Action
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Immediate Reset
Reserved
WDE
ADuC814
WDWR