EVAL-AD1954EB Analog Devices Inc, EVAL-AD1954EB Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD1954EB
• Description: BOARD EVAL FOR AD1954
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1954EB

• Rohs Status: RoHS non-compliant

Pin No.
(44-MQFP) (48-LQFP) Mnemonic
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
*For a complete description of the pins, refer to the Pin Functions section.
REV. A
1
2
3
4
5
6
7
8
9
Pin No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
NC
MCLK2
MCLK1
MCLK0
DEEMP/
SDATA_AUX
MUTE
DVDD
SDATA2
BCLK2
LRCLK2
SDATA1
BCLK1
DGND
LRCLK1
SDATA0
BCLK0
LRCLK0
CDATA
CCLK
CLATCH
RESETB
AVDD
AGND
NC
VOUTS–
VOUTS+
AGND
VOUTR–
VOUTR+
AVDD
AGND
AVDD
VOUTL+
VOUTL–
AGND
NC
NC
VREF
FILTCAP
ZEROFLAG OUT
SDATAOUT OUT
BCLKOUT
LRCLKOUT OUT
ODVDD
DCSOUT
COUT
MCLKOUT OUT
DGND
Input/
Output Description*
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
PIN FUNCTION DESCRIPTIONS
Auxiliary Serial Data Input
Analog 5 V Supply
Analog GND
Analog GND
Analog 5 V Supply
Analog GND
Analog 5 V Supply
Analog GND
No Connect
Master Clock Input 2 256 f
Master Clock Input 2 256 f
Master Clock Input 2 256 f /512 f
Master Clock Input 1 256 f
Master Clock Input 1 256 f
Master Clock Input 1 256 f /512 f
Master Clock Input 0 256 f
Master Clock Input 0 256 f
Master Clock Input 0 256 f /512 f
Enables 44.1 kHz De-emphasis Filter (Others Available through SPI Control)
Mute Signal. Initiates volume ramp-down.
Digital Supply for DSP Core, 4.5 V to 5.5 V
Serial Data Input 2
Bit Clock 2
Left/Right Clock 2
Serial Data Input 1
Bit Clock 1
Digital Ground
Left/Right Clock 1
Serial Data Input 0
Bit Clock 0
Left/Right Clock 0
SPI Data Input
SPI Data Bit Clock
SPI Data Framing Signal
Reset Signal, Active Low
No Connect
Negative Sub Analog DAC Output
Positive Sub Analog DAC Output
Negative Left Analog DAC Output
Positive Left Analog DAC Output
Positive Left Analog DAC Output
Negative Left Analog DAC Output
No Connect
No Connect
Connection for Filtered AVDD/2
Connection for Noise Reduction Capacitor
Zero Flag Output. High when both left and right channels are 0 for 1024 frames.
Serial Data Mux Output
Bit Clock Mux Output
Left/Right Clock Mux Output
Digital Supply Pin for Output Drivers, 2.5 V to 5.5 V
Data Capture Serial Output for Data Capture Registers. Use in conjunction with
selected LRCLK and BCLK to form a 3-wire output.
SPI Data Output. Three-stated when inactive.
Master Clock Output 512 f
Master Clock Output 512 f
Master Clock Output 512 f /256 f
Digital Ground
–7–
S
S
S
S
S
S
S
S
/256 f
/256 f (Frequency Selected by SPI Register)
/512 f
/512 f
/512 f
/512 f
/512 f
/512 f
S
S
S
S
S
S
S
S
AD1954