EVAL-AD1954EB Analog Devices Inc, EVAL-AD1954EB Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD1954EB
• Description: BOARD EVAL FOR AD1954
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1954EB

• Rohs Status: RoHS non-compliant

The initiate-safe-transfer Bit 9 will request a data transfer from
the SPI safeload registers to the parameter RAM. The safeload
registers contain address-data pairs, and only those registers
that have been written to since the last transfer operation will be
uploaded. The user may poll for this operation to complete by
reading Bit 0 of Control Register 1. The Safeload Mechanism
section goes into more detail on this feature.
Bit 10, the halt program bit, is used to initiate a volume ramp-down
followed by a shutdown of the DSP core. The user may poll for
this operation to complete by reading Bit 1 of Control Register 1.
Bit 11 sets the function of the de-emphasis/auxiliary serial input
pin. When this bit is set to 1, the pin will function as an auxiliary
serial input that is clocked by the input mux’s selected clocks.
When set to 0, this pin enables the 44.1 kHz de-emphasis curve.
Register Bits
11
10
9
8
7
6
5:4
3:2
1:0
Register Bits
1
0
Bit 0 is asserted when all requested safeload registers have been
transferred to the parameter RAM. It is cleared after the read
operation is complete.
Bit 1 is asserted after the requested shutdown of the DSP is com-
pleted. When this bit is set, the user is free to write or read any
RAM location without causing an audio pop or click.
REV. A
Table III. Control Register 1 Write Definition
Table IV. Control Register 1 Read Definition
Function
De-emphasis/Auxiliary Serial Input Pin Select
(1 = Auxiliary Serial Input)
Halt Program (1 = Halt)
Initiate Safe Transfer (1 = Transfer)
Enable DCSOUT Output Pin (1 = Enable)
Soft Mute (1 = Start Mute Sequence)
Soft Power-Down (1 = Power-Down)
De-emphasis Curve Select
00 = None
01 = 44.1 kHz
10 = 32 kHz
11 = 48 kHz
Serial in Mode
00 = I
01 = Right-Justified
10 = DSP
11 = Left-Justified
Word Length
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
Function
DSP Core Shutdown Complete
1 = Shutdown Complete
0 = Not Shut Down
Safe Memory Load Complete
1 = Complete (Note: Cleared after Read)
0 = Not Complete
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Register Bits
9
8
7:6
5:4
3
2
1:0
Control Register 2
Table V documents the contents of Control Register 2. Bits 1 and 0
set the frequency of the MCLKOUT pin. If these bits are set to
00, then the MCLKOUT pin is disabled (default).When set to
01, the MCLKOUT pin is set to 512  f
the internal master clock used by the DSP core.When set to 10,
this pin is set to 256  f
clock by 2. In this mode, the output 256 f
clock by 2. In this mode, the output 256 f
clock by 2. In this mode, the output 256 f clock will be inverted
with respect to the input 256 f
with respect to the input 256 f
with respect to the input 256 f clock. This is not the case with the
feedthrough mode.When set to 11, the MCLKOUT pin mirrors
the selected MCLK input pin (it’s the output of the MCLK mux
selector). Note that the internal DSP master clock may either be
the same as the selected MCLK pin (when MCLK frequency
select is set to 512  f
pin using an internal clock doubler (when MCLK frequency
select is set to 256  f
Bit 2 selects one of two possible MCLK input frequencies. When
set to 0 (default), the MCLK frequency is set to 512  f
mode, the internal DSP clock and the external MCLK are at the
same frequency. When set to 1, the MCLK frequency is set to
256  f
DSP clock.
Bits 5 and 4 select one of three clock input sources using an inter-
nal mux. To avoid click and pop noises when switching MCLK
sources, it is recommended that the user put the DSP core in
shutdown before switching MCLK sources.
Bits 7 and 6 select one of three serial input sources using an
internal mux. Each source selection includes a separate SDATA,
LRCLK, and BCLK input. To avoid click and pop noises when
switching serial sources, it is recommended that the user put the
DSP core in shutdown before writing to these bits.
f
f , and an internal clock doubler is used to generate the
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Table V. Control Register 2 Write Definition
Function
Volume Ramp Speed
1 = 160 ms Full Ramp Time
0 = 20 ms Full Ramp Time
Serial Port Output Enable
1 = Enabled
0 = Disabled
Serial Port Input Select
00 = IN0
01 = IN1
10 = IN2
11 = NA
MCLK Input Select
00 = MCLK0
01 = MCLK1
10 = MCLK2
11 = NA
Reserved
MCLK in Frequency Select
0 = 512  f
1 = 256  f
MCLK Out Frequency Select
00 = Disabled
01 = 512  f
10 = 256  f
11 = MCLK_Out = MCLK_In (Feedthrough)
f
f mode) or may be derived from the MCLK
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f
f , derived by dividing the internal DSP
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f
f
f
f
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f
f
f
f
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f
f , which is the same as
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AD1954
f
f . In this
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