MC56F8323EVME Freescale Semiconductor, MC56F8323EVME Datasheet - Page 77

BOARD EVALUATION MC56F8323

MC56F8323EVME

Manufacturer Part Number
MC56F8323EVME
Description
BOARD EVALUATION MC56F8323
Manufacturer
Freescale Semiconductor
Type
DSPr
Datasheets

Specifications of MC56F8323EVME

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC56F8322 and MC56F8323
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F83xx
Rohs Compliant
Yes
For Use With/related Products
MC56F8322, MC56F8323
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
5.6.14
5.6.14.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.14.2
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15
5.6.15.1
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
5.6.15.2
This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; for details, see
results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become
the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being
declared as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector
number of each IRQ, refer to
Freescale Semiconductor
Preliminary
Base + $D
Base + $E
RESET
RESET
Write
Write
Read
Read
Fast Interrupt 0 Vector Address High Register (FIVAH0)
Fast Interrupt 1 Match Register (FIM1)
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Reserved—Bits 15–5
Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
Reserved—Bits 15–7
Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0
15
15
0
0
0
0
Part
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
14
14
0
0
0
0
5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected
13
13
Table
0
0
0
0
12
12
0
0
0
0
4-3.
56F8323 Technical Data, Rev. 17
11
11
0
0
0
0
10
10
0
0
0
0
9
0
0
9
0
0
8
0
0
8
0
0
7
7
0
0
0
0
6
6
0
0
0
5
0
0
5
0
FAST INTERRUPT 1
4
4
0
0
VECTOR ADDRESS HIGH
FAST INTERRUPT 0
3
3
0
0
2
0
2
0
Register Descriptions
1
0
1
0
0
0
0
0
77

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