MC56F8323EVME Freescale Semiconductor, MC56F8323EVME Datasheet - Page 5

• Manufacturer Part Number: MC56F8323EVME
• Description: BOARD EVALUATION MC56F8323
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8323EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8322 and MC56F8323
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8322, MC56F8323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

56F8323/56F8123 General Description
Note: Features in italics are NOT available in the 56F8123 device.
Freescale Semiconductor
Preliminary
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM module
• Two 4-channel 12-bit ADCs
• Temperature Sensor
C-efficient architecture
3
3
4
4
5
4
2
3
6
TEMP_SENSE
Decoder 0 or
VREF
Current Sense Inputs
Fault Inputs
Quadrature
FlexCAN or
AD0
AD1
PWM Outputs
Timer A or
Timer C or
GPIO B
SCI0 or
GPIOC
GPIOC
Quad
Quad
Decoding
Peripherals
Program Memory
16K x 16 Flash
4K x 16 Flash
Data Memory
4K x 16 RAM
2K x 16 RAM
4K x 16 Boot
Memory
Flash
PWMA or
SPI1 or
GPIOA
SCI1 or
SPI0 or
GPIOB
56F8323/56F8123 Block Diagram
4
Device Selects
56F8323 Technical Data, Rev. 17
Program Controller
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
Peripheral
and Hardware
Looping Unit
RESET
PAB
CDBR
CDBW
PDB
IPBus Bridge (IPBB)
Control
EOnCE
5
JTAG/
Port
RW
Generation Unit
Watchdog
COP/
Address
OCR_DIS
IPAB
56800E Core
• One Quadrature Decoder
• One FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
• Up to 27 GPIO lines
• 64-pin LQFP Package
Controller
Interrupt
IPWDB
IRQA
16-Bit
unobtrusive, real-time debugging
4
V
System Bus
CAP
Three 16-bit Input Registers
16 x 16 + 36 −> 36-Bit MAC
Four 36-bit Accumulators
Control
4
V
Digital Reg
IPRDB
DD
Data ALU
Integration
System
4
Module
R/W Control
V
Low Voltage
Supervisor
SS
resets
Clock
2
V
Analog Reg
DDA
P
O
R
Relaxation Oscillator
Manipulation
Generator*
V
*Includes On-Chip
SSA
Clock
Unit
Bit
PLL
O
C
S
XTAL or GPIOC
EXTAL or GPIOC
5