MC56F8323EVME Freescale Semiconductor, MC56F8323EVME Datasheet - Page 58
MC56F8323EVME
Manufacturer Part Number
MC56F8323EVME
Description
BOARD EVALUATION MC56F8323
Manufacturer
Freescale Semiconductor
Type
DSPr
Specifications of MC56F8323EVME
Contents
Module and Misc Hardware
Processor To Be Evaluated
MC56F8322 and MC56F8323
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F83xx
Rohs Compliant
Yes
For Use With/related Products
MC56F8322, MC56F8323
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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5.3.3
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
fast interrupts before the core does.
A fast interrupt is defined (to the ITCN) by:
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
58
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
Fast Interrupt Handling
1. See IPIC field definition in Section 5.6.30.2
00
01
10
11
IPIC_LEVEL[1:0]
Table 5-2. Interrupt Priority Encoding
56F8323 Technical Data, Rev. 17
1
No Interrupt or SWILP
Priority 0
Priority 1
Priorities 2 or 3
Current Interrupt
Priority Level
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Exception Priority
Required Nested
Freescale Semiconductor
Preliminary
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