C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 97
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
- Current page: 97 of 302
- Download datasheet (3Mb)
C8051F55x/56x/57x
12.3. SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts. In this
example, the SFR Control register is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51
is executing in-line code that is writing values to SPI Data Register (SFR “SPI0DAT”, located at address
0xA3 on SFR Page 0x00). The device is also using the CAN peripheral (CAN0) and the Programmable
Counter Array (PCA0) peripheral to generate a PWM output. The PCA is timing a critical control function in
its interrupt service and so its associated ISR that is set to high priority. At this point, the SFR page is set to
access the SPI0DAT SFR (SFRPAGE = 0x00). See Figure 12.2.
SFR Page
Stack SFR's
0x0
SFRPAGE
(SPI0DAT)
SFRNEXT
SFRLAST
Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT
Rev. 1.1
97
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