C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 177

• Manufacturer Part Number: C8051F560-TB
• Description: BOARD PROTOTYPE W/C8051F560
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F560-TB

• Contents: Board
• Processor To Be Evaluated: C8051F56x
• Processor Series: C8051F56x
• Interface Type: USB
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V to 5.25 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F55x, C8051F56x, C8051F57x
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1694

19.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0, P1, P2 or P3.
A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values
of P0, P1, P2, and P3. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer
match the software controlled value. This allows Software to be notified if a certain change or pattern
occurs on P0, P1, P2, or P3 input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which of the port pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (Pn & PnMASK) does not equal
(PnMATCH & PnMASK), where n is 0, 1, 2 or 3
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
SFR Definition 19.4. P0MASK: Port 0 Mask Register
SFR Address = 0xF2; SFR Page = 0x00
SFR Definition 19.5. P0MAT: Port 0 Match Register
SFR Address = 0xF1; SFR Page = 0x00
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P0MASK[7:0]
P0MAT[7:0]
Name
Name
7
0
7
1
Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MAT which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
6
0
6
1
5
0
5
1
Rev. 1.1
P0MASK[7:0]
4
0
4
1
P0MAT[7:0]
R/W
R/W
Function
Function
3
0
3
1
C8051F55x/56x/57x
2
0
2
1
1
0
1
1
0
0
0
1
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