C8051F560-TB Silicon Laboratories Inc, C8051F560-TB Datasheet - Page 157
C8051F560-TB
Manufacturer Part Number
C8051F560-TB
Description
BOARD PROTOTYPE W/C8051F560
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.TOOLSTICK560DC.pdf
(302 pages)
Specifications of C8051F560-TB
Contents
Board
Processor To Be Evaluated
C8051F56x
Processor Series
C8051F56x
Interface Type
USB
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V to 5.25 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1694
- Current page: 157 of 302
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18.2. Programmable Internal Oscillator
All C8051F55x/56x/57x devices include a programmable internal high-frequency oscillator that defaults as
the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICRS and
OSCIFIN registers defined in SFR Definition 18.3 and SFR Definition 18.4. On C8051F55x/56x/57x
devices, OSCICRS and OSCIFIN are factory calibrated to obtain a 24 MHz base frequency. Note that the
system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64, or
128, as defined by the IFCN bits in register OSCICN. The divide value defaults to 128 following a reset.
18.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to SUSPEND.
Note: When entering suspend mode, firmware must set the ZTCEN bit in REF0CN (SFR Definition 7.1).
Port 0 Match Event.
Port 1 Match Event.
Port 2 Match Event.
Port 3 Match Event.
Comparator 0 enabled and output is logic 0.
Rev. 1.1
C8051F55x/56x/57x
157
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