ST7MDT2-EPB2/US STMicroelectronics, ST7MDT2-EPB2/US Datasheet - Page 49
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ST7MDT2-EPB2/US
Manufacturer Part Number
ST7MDT2-EPB2/US
Description
BOARD PROGRAMMING SGL POS ST7
Manufacturer
STMicroelectronics
Type
MCUr
Specifications of ST7MDT2-EPB2/US
Contents
Programmer Board
For Use With/related Products
ST72311, ST72124, ST72314, ST72334
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 49 of 153
- Download datasheet (3Mb)
14 ON-CHIP PERIPHERALS
14.1 WATCHDOG TIMER (WDG)
14.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
14.1.2 Main Features
Figure 29. Watchdog Block Diagram
Programmable timer (64 increments of 12288
CPU cycles)
Programmable reset
Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
f
CPU
WDGA
RESET
T6
T5
WATCHDOG CONTROL REGISTER (CR)
7-BIT DOWNCOUNTER
CLOCK DIVIDER
T4
12288
T3
14.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
T2
Hardware Watchdog selectable by option byte
Watchdog Reset indicated by status flag (in
versions with Safe Reset option only)
ST72334J/N, ST72314J/N, ST72124J
T1
T0
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