ST7MDT2-EPB2/US STMicroelectronics, ST7MDT2-EPB2/US Datasheet - Page 35

• Manufacturer Part Number: ST7MDT2-EPB2/US
• Description: BOARD PROGRAMMING SGL POS ST7
• Manufacturer: STMicroelectronics
• Type: MCUr

Specifications of ST7MDT2-EPB2/US

• Contents: Programmer Board
• For Use With/related Products: ST72311, ST72124, ST72314, ST72334
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11 POWER SAVING MODES
11.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see
TIVE HALT and HALT.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 19. Power Saving Mode Transitions
Figure
19): SLOW, WAIT (SLOW WAIT), AC-
ACTIVE HALT
SLOW WAIT
POWER CONSUMPTION
SLOW
HALT
WAIT
RUN
Low
High
CPU
).
11.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
– To adapt the internal clock frequency (f
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ing the WAIT mode while the device is already in
SLOW mode.
Figure 20. SLOW Mode Clock Transitions
internal clock in the device,
the available supply voltage.
ST72334J/N, ST72314J/N, ST72124J
CP1:0
f
SMS
f
OSC
CPU
/2
FREQUENCY
00
f
NEW SLOW
OSC
REQUEST
/4
01
CPU
f
OSC
NORMAL RUN MODE
).
/8
REQUEST
CPU
f
OSC
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) to
/2