EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 78

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

ADuC832
TIMER 3 GENERATED BAUD RATES
The high integer dividers in a UART block mean that high
speed baud rates are not always possible using some particular
crystals. For example, using a 12 MHz crystal, a baud rate of
115,200 is not possible. To address this problem, the ADuC832
has a dedicated baud rate timer (Timer 3) specifically for
generating highly accurate baud rates.
Timer 3 can be used instead of Timer 1 or Timer 2 for generating
very accurate high speed UART baud rates including 115,200
and 230,400. Timer 3 also allows a much wider range of baud
rates to be obtained. Every desired bit rate from 12 bits/sec to
393,216 bits/sec can be generated to within an error of ±0.8%.
Timer 3 also frees up the other three timers, allowing them to
be used for different applications. A block diagram of Timer 3 is
shown in Figure 84.
Two SFRs (T3CON and T3FD) are used to control Timer 3.
T3CON is the baud rate control SFR, allowing Timer 3 to be
used to set up the UART baud rate, and setting up the binary
divider (DIV).
FRACTIONAL
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON.
DIVIDER
CORE
CLK
*
÷ (1 + T3FD/64)
÷2
OSC. FREQ. IS DIVIDED BY 2, NOT 12.
NOTE AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
*
÷16
CORE CLK IS DEFINED BY THE CD BITS IN PLLCON.
Figure 84. Timer 3, UART Baud Rates
÷2
DIV
TRANSITION
T2EX
DETECTOR
PIN
PIN
CORE
CLK
T2
*
T3 RX/TX
CLOCK
RX CLOCK (FIG 83)
TIMER 1/TIMER 2
2
1
1
TX CLOCK (FIG 83)
0
0
C/T2 = 0
C/T2 = 1
TIMER 1/TIMER 2
EXEN2
CONTROL
T3EN
CONTROL
TR2
TX CLOCK
RX
CLOCK
Figure 83. Timer 2, UART Baud Rates
EXF 2
Rev. A | Page 78 of 92
RCAP2L
(8 BITS)
TL2
TIMER 2
INTERRUPT
RCAP2H
(8 BITS)
TH2
Table 43. T3CON SFR Bit Designations
Bit
[7]
[6:4]
[2:0]
The appropriate value to write to the DIV[2:0] bits can be
calculated using the following formula
where f
Note that the DIV value must be rounded down.
T3FD is the fractional divider ratio required to achieve the
required baud rate. The appropriate value for T3FD can be
calculated using the following formula:
Note that T3FD should be rounded to the nearest integer.
RELOAD
OVERFLOW
T
DIV
TIMER 2
3
Name
T3BAUDEN
Reserved
DIV[2:0]
CORE
FD
=
=
is defined in the PLLCON SFR, PLLCON[2:0].
log
2
DIV
⎛
⎜
⎜
⎝
32
2
1
1
×
×
×
log(
Baud
OVERFLOW
Description
T3 UART baud rate enable. Set to enable
Timer 3 to generate the baud rate. When
set, PCON[7], T2CON[4], and T2CON[5] are
ignored. Cleared to let the baud rate be
generated as per a standard 8052.
Binary divider factor
DIV2
0
0
0
0
1
1
1
1
2
Baud
f
f
CORE
TIMER 1
0
CORE
) 2
0
0
Rate
Rate
1
DIV1
0
0
1
1
0
0
1
1
RCLK
TCLK
⎞
⎟
⎟
⎠
16
16
SMOD
DIV0
0
1
0
1
0
1
0
1
RX
CLOCK
TX
CLOCK
Binary Divider
1
1
1
1
1
1
1
1