EVAL-ADUC7026QSPZ Analog Devices Inc, EVAL-ADUC7026QSPZ Datasheet - Page 79

• Manufacturer Part Number: EVAL-ADUC7026QSPZ
• Description: KIT DEV ADUC7026/7027 QUICK PLUS
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7026QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7026
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7026
• Lead Free Status / Rohs Status: Compliant

T2CLRI Register
Name
T2CLRI
T2CLRI is an 8-bit register. Writing any value to this register
clears the Timer2 interrupt.
Timer3 (Watchdog Time)
Timer3 has two modes of operation, normal mode and
watchdog mode. The watchdog timer is used to recover from
an illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a processor reset.
Normal Mode
Timer3 in normal mode is identical to Timer0, except for the
clock source and the count-up functionality. The clock source is
32 kHz from the PLL and can be scaled by a factor of 1, 16, or
256 (see Figure 67).
Watchdog Mode
Watchdog mode is entered by setting Bit 5 in the T3CON MMR.
Timer3 decreases from the value present in the T3LD register
until 0. T3LD is used as the timeout. The maximum timeout can
be 512 sec using the prescaler/256, and full-scale in T3LD.
Timer3 is clocked by the internal 32 kHz crystal when operating
in the watchdog mode. Note that to enter watchdog mode
successfully, Bit 5 in the T3CON MMR must be set after
writing to the T3LD MMR.
If the timer reaches 0, a reset or an interrupt occurs, depending
on Bit 1 in the T3CON register. To avoid reset or interrupt, any
value must be written to T3CLRI before the expiration period.
This reloads the counter with T3LD and begins a new timeout
period.
When watchdog mode is entered, T3LD and T3CON are write-
protected. These two registers cannot be modified until a reset
clears the watchdog enable bit, which causes Timer3 to exit
watchdog mode.
The Timer3 interface consists of four MMRs: T3LD, T3VAL,
T3CON, and T3CLRI.
T3LD Register
Name
T3LD
T3LD is a 16-bit register load register.
32.768kHz
Address
0xFFFF034C
Address
0xFFFF0360
Figure 67. Timer3 Block Diagram
PRESCALER
/1, 16 OR 256
Default Value
0xFF
Default Value
0x0000
COUNTER
UP/DOWN
TIMER3
VALUE
16-BIT
16-BIT
LOAD
WATCHDOG
RESET
TIMER3 IRQ
Access
W
Access
R/W
Rev. B | Page 79 of 92
T3VAL Register
Name
T3VAL
T3VAL is a 16-bit read-only register that represents the current
state of the counter.
T3CON Register
Name
T3CON
T3CON is the configuration MMR described in Table 78.
Table 78. T3CON MMR Bit Descriptions
Bit
31:9
8
7
6
5
4
3:2
1
0
T3CLRI Register
Name
T3CLRI
T3CLRI is an 8-bit register. Writing any value to this register on
successive occassions clears the Timer3 interrupt in normal
mode or resets a new timeout period in watchdog mode .
Note that the user must perform successive writes to this
register to ensure resetting the timeout period.
ADuC7019/20/21/22/24/25/26/27/28
Value
00
01
10
11
Address
0xFFFF0364
Address
0xFFFF0368
Address
0xFFFF036C
Description
Reserved.
Count Up. Set by user for Timer3 to count up.
Cleared by user for Timer3 to count down by
default.
Timer3 Enable Bit. Set by user to enable Timer3.
Cleared by user to disable Timer3 by default.
Timer3 Mode. Set by user to operate in
periodic mode. Cleared by user to operate
in free-running mode. Default mode.
Watchdog Mode Enable Bit. Set by user to
enable watchdog mode. Cleared by user to
disable watchdog mode by default.
Secure Clear Bit. Set by user to use the secure
clear option. Cleared by user to disable the
secure clear option by default.
Prescale.
Source Clock/1 by Default.
Source Clock/16.
Source Clock/256.
Undefined. Equivalent to 00.
Watchdog IRQ Option Bit. Set by user to
produce an IRQ instead of a reset when
the watchdog reaches 0. Cleared by user to
disable the IRQ option.
Reserved.
Default Value
0xFFFF
Default Value
0x0000
Default Value
0x00
Access
R
Access
R/W
Access
W