EVAL-ADUC7128QSPZ Analog Devices Inc, EVAL-ADUC7128QSPZ Datasheet - Page 9

KIT DEV FOR ADUC7128

EVAL-ADUC7128QSPZ

Manufacturer Part Number
EVAL-ADUC7128QSPZ
Description
KIT DEV FOR ADUC7128
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet

Specifications of EVAL-ADUC7128QSPZ

Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
Silicon Manufacturer
Analog Devices
Core Architecture
ARM
Core Sub-architecture
ARM7TDMI
Silicon Core Number
ADuC7128
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ADuC7128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Table 3. External Memory Read Cycle
Parameter
CLK
t
t
t
t
t
t
t
t
t
t
t
MS_AFTER_CLKH
ADDR_AFTER_CLKH
AE_H_AFTER_MS
AE
HOLD_ADDR_AFTER_AE_L
RD_L_AFTER_AE_L
RD_H_AFTER_CLKH
RD
DATA_BEFORE_RD_H
DATA_AFTER_RD_H
RELEASE_WS_AFTER_RD_H
A/D[15:0]
ECLK
XA16
BHE
GP0
BLE
WS
AE
RS
0ns
FFFF
t
MS_AFTER_CLKH
CLK
t
ADDR_AFTER_CLKH
50ns
t
AE_H_AFTER_MS
Min
1/MD Clock
4
4
0
16
8
SAMPLE_ADDR_0
2348
t
AE
100ns
t
RD_L_AFTER_AE_L
XXXX CDEF XX
t
t
HOLD_ADDR_AFTER_AE_L
RD
Figure 4. External Memory Read Cycle
Typ
ns typ × (CDPOWCON[2:0] + 1)
½ CLK
(XMxPAR[14:12] + 1) × CLK
½ CLK + (! XMxPAR[10] ) × CLK
½ CLK + (! XMxPAR[10]+ ! XMxPAR[9] ) × CLK
(XMxPAR[3:0] + 1) × CLK
+ (! XMxPAR[9]) × CLK
1 × CLK
SAMPLE_DATA_L
150ns
t
RD_H_AFTER_CLKH
t
DATA_BEFORE_RD_H
t
Rev. 0 | Page 9 of 92
DATA_AFTER_RD_H
SAMPLE_ADDR_1
200ns
234A
250ns
XX
SAMPLE_DATA_H
300ns
ADuC7128/ADuC7129
Max
8
16
4
89AB
t
RELEASE_WS_AFTER_RD_H
350ns
Unit
ns
ns
ns
ns
400ns

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