EVAL-ADUC7128QSPZ Analog Devices Inc, EVAL-ADUC7128QSPZ Datasheet - Page 13

• Manufacturer Part Number: EVAL-ADUC7128QSPZ
• Description: KIT DEV FOR ADUC7128
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7128QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7128
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 7. SPI Slave Mode Timing (PHASE Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
2
CS
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
SFS
t
t
UCLK
HCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
depends on the clock divider or CD bits in the PLLCON MMR, t
(POLARITY = 0)
(POLARITY = 1)
SCLOCK
SCLOCK
Description
CS to SCLOCK edge
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
CS high after SCLOCK edge
MISO
MOSI
CS
t
CS
1
t
t
DSU
DAV
2
2
t
SH
Figure 8. SPI Slave Mode Timing (PHASE Mode = 1)
MSB IN
HCLK
t
DHD
t
MSB
= t
1
SL
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UCLK
1
t
DF
/2
CD
Min
2 × t
1 × t
2 × t
0
.
UCLK
UCLK
UCLK
t
BIT 6 TO BIT 1
DR
BIT 6 TO BIT 1
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
t
SR
HCLK
HCLK
LSB IN
t
SF
Max
2 × t
12.5
12.5
12.5
12.5
LSB
ADuC7128/ADuC7129
t
SFS
HCLK
+ 2 × t
UCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns